micheleandCursor
a28120b44e
Refresh BOM (2026-07-09 CSV), Gerbers, EasyEDA project, pick-and-place, and schematic export; document corrected ADAU crystal/PLL strapping and Si4684 reference clock in the manual; add PCBWay acknowledgement on the back cover only. Co-authored-by: Cursor <cursoragent@cursor.com>
279 lines
11 KiB
TeX
279 lines
11 KiB
TeX
\chapter{DSP Configuration (SigmaStudio)}
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\label{ch:sigmastudio}
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This chapter documents how the ADAU1701 is configured in SigmaStudio: the
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hardware settings that must match the board, the audio signal-processing
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chain, and the parameters exposed for runtime control by the ESP32. The
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resulting SigmaStudio export is what the host writes into the DSP's RAM at
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every boot (Section~\ref{sec:hw-adau}). For the firmware driver, safeload
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API, persistence, and HTTP usage, see Chapter~\ref{ch:adau1701}.
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\section{Overview}
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\label{sec:ss-overview}
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The DSP program is built once in SigmaStudio and exported as a sequence of
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register writes. Because the board carries no self-boot EEPROM, the ESP32
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replays that sequence over I\textsuperscript{2}C (address 0x34) on every
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power-up. SigmaStudio is therefore used purely to \emph{design and export}
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the program, not to drive the chip in operation.
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\begin{drkey}[No hardware required to export]
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The whole program can be built and exported offline, without a physical
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ADAU1701 or a USBi programmer connected. A USBi block is placed in the
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Hardware Configuration only because SigmaStudio requires a communication
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channel to compile; it is never used for a real download in this project.
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\end{drkey}
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\section{Hardware Configuration}
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\label{sec:ss-hwcfg}
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The Hardware Configuration tab must mirror the board exactly. The key
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settings are collected in Table~\ref{tab:ss-hwcfg}. The 48\,kHz system
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sample rate follows from the \textbf{board strapping}, not from a
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SigmaStudio preference alone: X1 is a 12.288\,MHz crystal, PLL\_MODE selects
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256\,$\times$\,f\textsubscript{S}, and 12.288\,MHz\,/\,256 = 48\,kHz.
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\begin{table}[htbp]
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\centering
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\begin{tabular}{@{}L{4.2cm}L{9.2cm}@{}}
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\drhead Setting & Value \\
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\midrule
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Control port (I\textsuperscript{2}C address) & 0x34 (ADDR0/ADDR1 = GND) \\
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Self-boot & Disabled (host RAM load) \\
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System sample rate & 48\,kHz (256\,$\times$\,f\textsubscript{S} strapping) \\
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MCLK & 12.288\,MHz crystal (256\,$\times$\,f\textsubscript{S}) \\
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Serial Input format & I\textsuperscript{2}S, 24-bit \\
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Serial Output & \textbf{Master Mode} (ADAU generates clocks) \\
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Word length & 24 bits \\
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RAM Modulo / Program Length & 1x (1024 instructions) \\
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\bottomrule
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\end{tabular}
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\caption{ADAU1701 hardware settings in SigmaStudio.}
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\label{tab:ss-hwcfg}
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\end{table}
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\begin{drnote}[Clock source on the board]
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SigmaStudio's 48\,kHz sample-rate field must agree with the fabricated
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hardware: passive crystal X1 (12.288\,MHz, CL = 12\,pF) on MCLKI/OSCO with
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22\,pF load caps, PLL\_MODE0 = GND and PLL\_MODE1 = 3V3 (256\,$\times$\,f\textsubscript{S}).
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The ADAU1701 internal oscillator multiplies the crystal; it is not an active
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oscillator module. See Chapter~\ref{ch:hardware}, Section~\ref{sec:hw-val-adau}.
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\end{drnote}
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\subsection{Multipurpose pin (MP) assignment}
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The ADAU1701 multipurpose pins are assigned to the serial audio signals
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as wired on the board. Table~\ref{tab:ss-mp} lists the assignment; it
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matches the board GPIO map (Section~\ref{sec:hw-gpio}).
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\begin{table}[htbp]
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\centering
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\begin{tabular}{@{}L{2.4cm}L{3.6cm}L{7.2cm}@{}}
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\drhead MP pin & Direction / function & Signal \\
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\midrule
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MP0 & Input Sdata\_in0 & audio from Si4684 (radio) \\
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MP1 & Input Sdata\_in1 & audio from ESP32 \\
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MP4 & Input Lrclk\_in & LRCLK (returned via board link) \\
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MP5 & Input Bclk\_in & BCLK (returned via board link) \\
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MP6 & Output Sdata\_out0 & audio to FSC-BT1035 \\
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MP10 & Lrclk\_out & LRCLK generated (master) \\
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MP11 & Bclk\_out & BCLK generated (master) \\
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\bottomrule
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\end{tabular}
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\caption{Multipurpose pin assignment. MP2, MP3, MP7--MP9 are unused
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(GPIO input, default).}
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\label{tab:ss-mp}
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\end{table}
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\begin{drnote}[Master clock routing]
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The ADAU1701 is the I\textsuperscript{2}S master: it generates LRCLK and
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BCLK on MP10/MP11. On the board these are wired to MP4/MP5, so the same
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master clocks time the serial inputs. This shared-clock scheme means the
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serial inputs are configured as \emph{clock inputs} even though the ADAU
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itself is master --- the clocks originate at MP10/MP11 and return through
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the board link. All companion chips (Si4684, ESP32, BT1035) are
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I\textsuperscript{2}S slaves.
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\end{drnote}
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\section{Signal-processing chain}
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\label{sec:ss-chain}
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The audio flows through a fully stereo chain, built in the Schematic tab
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(Figure~\ref{fig:ss-chain}). Two stereo sources are level-trimmed, mixed,
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equalised, volume-controlled, and peak-limited before reaching the two
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digital outputs that feed the Bluetooth module.
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=\linewidth]{sigma-chain.jpg}
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\caption{The complete stereo signal-processing chain in SigmaStudio:
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Input \(\rightarrow\) source faders \(\rightarrow\) stereo mixer
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\(\rightarrow\) parametric EQ \(\rightarrow\) master volume
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\(\rightarrow\) per-channel limiters \(\rightarrow\) outputs.}
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\label{fig:ss-chain}
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\end{figure}
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\subsection{Block-by-block}
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\begin{table}[htbp]
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\centering
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\small
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\begin{tabular}{@{}L{2.4cm}L{3.6cm}L{7.2cm}@{}}
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\drhead Stage & Block & Role \\
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\midrule
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Input & Input (ch. 2--5) & radio L/R, ESP32 L/R \\
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Source trim & Si4674, ESP32 faders & per-source stereo level \\
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Mix & Stereo Mixer & combine sources, keep L/R \\
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EQ & Parametric EQ (2-ch) & high-pass + 5 peaking bands \\
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Volume & Multiple volume (2-ch) & master volume \\
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Protect & Limiter 1 / Limiter 2 & per-channel peak limiting \\
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Output & Output (DIG0, DIG1) & L/R to FSC-BT1035 \\
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\bottomrule
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\end{tabular}
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\caption{Signal-processing blocks and their roles. The chain is stereo
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end to end; L and R never collapse to mono.}
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\label{tab:ss-blocks}
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\end{table}
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\subsection{Signal flow}
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\begin{drcode}[Signal flow (stereo)]
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Input ch2/3 (radio L/R) -> Si4674 fader --.
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|-> Stereo Mixer -> Param EQ
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Input ch4/5 (ESP32 L/R) -> ESP32 fader --'
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-> Master Volume -> Limiter L / Limiter R -> Output DIG0 / DIG1 -> BT1035
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\end{drcode}
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\section{Equaliser}
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\label{sec:ss-eq}
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The parametric EQ is a two-channel (stereo) block; a single set of bands
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applies identically to L and R. It is configured with one high-pass and
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five peaking bands, all starting flat (0\,dB) so the default response is
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neutral and any tone shaping is an explicit choice made at runtime by the
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firmware.
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\begin{table}[htbp]
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\centering
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\footnotesize
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\begin{tabular}{@{}L{1.4cm}L{2.4cm}L{2.2cm}L{1.6cm}L{1.2cm}@{}}
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\drhead Band & Type & Frequency & Gain & Q \\
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\midrule
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1 & HP Butterworth & 20\,Hz & --- & 1.41 \\
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2 & Peaking & 100\,Hz & 0\,dB & 1.0 \\
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3 & Peaking & 400\,Hz & 0\,dB & 1.0 \\
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4 & Peaking & 1\,kHz & 0\,dB & 1.0 \\
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5 & Peaking & 3\,kHz & 0\,dB & 1.0 \\
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6 & Peaking & 8\,kHz & 0\,dB & 1.0 \\
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\bottomrule
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\end{tabular}
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\caption{Parametric EQ bands. Band~1 removes DC and subsonic content;
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bands 2--6 are the tone controls the firmware adjusts.}
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\label{tab:ss-eq}
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\end{table}
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\begin{drnote}[Double precision for the high-pass]
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The high-pass sits at 20\,Hz, very low relative to the 48\,kHz sample
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rate, so it uses a double-precision second-order block to avoid
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coefficient-quantisation noise in the bass. The peaking bands can use
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single precision.
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\end{drnote}
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\section{Master volume and limiters}
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\label{sec:ss-vol}
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A two-channel volume block provides the master level (0\,dB default). Two
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single-channel limiters --- one per channel --- protect the FSC-BT1035
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input from clipping on peaks. Suggested limiter settings are in
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Table~\ref{tab:ss-lim}.
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\begin{table}[htbp]
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\centering
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\begin{tabular}{@{}L{4.2cm}L{9.2cm}@{}}
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\drhead Parameter & Value \\
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\midrule
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RMS TC & 50\,dB/s \\
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Decay & 12\,dB/s \\
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Threshold & $-1$\,dB (protective) \\
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\bottomrule
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\end{tabular}
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\caption{Per-channel limiter settings. The limiter is left fixed (not
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runtime-adjustable).}
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\label{tab:ss-lim}
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\end{table}
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\section{Runtime-controllable parameters}
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\label{sec:ss-runtime}
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The firmware controls a subset of the DSP at runtime via safeload writes.
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These are the parameter cells whose addresses must be recorded from the
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SigmaStudio export (Section~\ref{sec:ss-export}).
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\begin{table}[htbp]
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\centering
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\begin{tabular}{@{}L{2.4cm}L{3.6cm}L{7.2cm}@{}}
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\drhead Control & Block & Runtime-adjustable \\
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\midrule
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Source levels (2) & Si4674 / ESP32 faders & yes \\
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EQ bands 2--6 & Parametric EQ & yes (gain/freq/Q) \\
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Master volume & Multiple volume & yes \\
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High-pass (band 1) & Parametric EQ & fixed \\
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Limiters & Limiter 1 / 2 & fixed \\
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\bottomrule
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\end{tabular}
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\caption{Parameters exposed to the firmware. Fixed blocks are set once
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in the program and never written at runtime.}
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\label{tab:ss-runtime}
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\end{table}
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\section{Virtual enhancements (stereo depth and bass boost)}
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\label{sec:ss-enhancements}
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The SigmaStudio export does not include dedicated stereo widener or bass
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boost blocks. Firmware maps enhancement levels (0--100) onto the
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existing Param EQ1 bands at runtime:
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\begin{itemize}
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\item \textbf{Bass enhance} --- peaking boost at 100\,Hz (+9\,dB max)
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and 400\,Hz (+3\,dB max).
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\item \textbf{Stereo enhance} --- slight 1\,kHz cut, plus 3\,kHz and
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8\,kHz lift for a wider, more present image. This is a
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psychoacoustic curve, not mid/side processing.
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\end{itemize}
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Enhancement levels are stored in \texttt{AudioProfile::enhancements} and
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applied by \texttt{core::applyEnhancementsToEq()} before safeload. Base EQ
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band settings in NVS are preserved; overlays replace affected bands only
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while the corresponding level is greater than zero.
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\begin{drcaution}[Use safeload for live changes]
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All runtime updates to the volume, source levels, and EQ bands must go
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through the ADAU1701 safeload mechanism. Writing parameter cells directly
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while audio is playing produces audible clicks.
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\end{drcaution}
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\section{Exporting the program}
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\label{sec:ss-export}
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With the schematic complete, the program is exported for the firmware:
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\begin{enumerate}
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\item Enable \emph{Action \(\rightarrow\) Enable Short Parameter Name
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for Export} so the exported cell names are concise.
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\item \emph{Action \(\rightarrow\) Export System Files}, and choose an
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output folder.
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\end{enumerate}
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The export produces the program data (control registers, program RAM, and
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parameter RAM) as byte sequences, plus the symbolic parameter addresses.
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The firmware's ADAU1701 driver replays the program data over
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I\textsuperscript{2}C at boot, and uses the parameter addresses for
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safeload updates.
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\begin{drnote}[No download needed]
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Since there is no ADAU1701 attached during development, do \emph{not} use
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\emph{Link Compile Download} (it would fail trying to reach the chip).
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\emph{Export System Files} compiles the schematic and writes the files
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directly.
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\end{drnote}
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