Sync hardware deliverables and manual after pre-fab design review.

Refresh BOM (2026-07-09 CSV), Gerbers, EasyEDA project, pick-and-place, and schematic export; document corrected ADAU crystal/PLL strapping and Si4684 reference clock in the manual; add PCBWay acknowledgement on the back cover only. Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-09 15:53:27 +02:00
parent fcda4ef151
commit a28120b44e
15 changed files with 28197 additions and 100 deletions
@@ -0,0 +1,41 @@
+No.;Quantity;Comment;Designator;MPN;Footprint;Part Name;LCSC;Category;ANNOTATION
+1;15;100nF;C1,C3,C8,C10,C11,C28,C30,C31,C32,C34,C36,C37,C38,C42,C48;CL05B104KB54PNC;C0402;100nF ±10% 50V;C307331;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+2;7;10uF;C2,C29,C33,C35,C40,C43,C47;GRM21BR61H106KE43L;C0805;10uF ±10% 50V;C440198;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+3;3;22uF;C4,C5,C9;CL21A226MAQNNNE;C0805;22uF ±20% 25V;C45783;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+4;7;1uF;C6,C7,C12,C17,C23,C26,C27;HGC0402R5105K500NTEJ;C0402;1uF ±10% 25V,1uF ±10% 50V;C7472948;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+5;1;33pF;C13;CL05C330JB5NNNC;C0402;33pF ±5% 50V;C70465;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+6;1;2.7pF;C14;GJM1555C1H2R7BB01D;C0402;±0.1pF 2.7pF 50V;C76904;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+7;3;8.2pF;C15,C21,C24;CSA0402C0G8R2B500GT;C0402;8.2pF 50V;C48642899;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+8;3;2.2nF;C16,C22,C25;CC0402KRX7R8BB222;C0402;2.2nF ±10% 25V;C541386;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+9;1;47nF;C39;CC0402KRX7R9BB473;C0402;47nF ±10% 50V;C272875;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+10;2;22pF;C41,C46;0402CG220J500NT;C0402;22pF ±5% 50V;C1555;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+11;1;3.3nF;C44;CC0402KRX7R9BB332;C0402;3.3nF ±10% 50V;C107028;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+12;1;56nF;C45;CGA0402X7R563K160GT;C0402;56nF ±10% 16V;C36911349;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+13;2;15pF;C49,C50;0402CG150J500NT;C0402;15pF ±5% 50V;C1548;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+14;1;8.2pF;C51;CC0603CPNPO9BN8R2;C0603;±0.25pF 8.2pF 50V;C3847265;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+15;1;2.2nF;C52;0603B222K500NT;C0603;2.2nF ±10% 50V;C1604;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+16;1;1uF;C53;CL10A105KB8NNNC;C0603;1uF ±10% 50V;C15849;Capacitors:Multilayer Ceramic Capacitors MLCC - SMD/SMT;
+17;1;ZX-XH2.54-4PWZ;CN1;ZX-XH2.54-4PWZ;CONN-TH_4P-P2.50_ZX-XH2.54-4PWZ;1x4P 间距:2.5mm 弯插 系列:XH;C7429643;Connectors:Wire To Board Connector;
+18;1;SS34;D1;SS34;SMA_L4.3-W2.6-LS5.2-RD;电压:40V 电流:3A;C8678;Diodes:Schottky Diodes;
+19;1;SRV05-4;D2;SRV05-4;SOT-23-6_L2.9-W1.6-P0.95-LS2.8-BL;单向ESD 5V截止 峰值脉冲电流：3A;C558418;Circuit Protection:ESD and Surge Protection (TVS/ESD);
+20;1;BAV99,215;D3;BAV99,215;SOT-23-3_L2.9-W1.6-P1.90-LS2.8-BR;100V 215mA;C2500;Diodes:Switching Diodes;
+21;1;18nH;L1;LQG15HS18NJ02D;L0402-RD;18nH ±5%;C86060;Inductors, Coils, Chokes:Inductors (SMD);
+22;1;22nH;L2;LQW15AN22NH00D;IND-SMD_L1.0-W0.5-2;22nH ±3%;C703122;Inductors, Coils, Chokes:Power Inductors;
+23;1;120nH;L3;LQW15ANR12J00D;L0402;120nH ±5%;C113123;Inductors, Coils, Chokes:Power Inductors;
+24;3;2kΩ;R1,R16,R19;0402WGF2001TCE;R0402;2kΩ ±1% 62.5mW 厚膜电阻;C4109;Resistors:Chip Resistor - Surface Mount;
+25;7;10kΩ;R2,R5,R6,R7,R8,R12,R13;0402WGF1002TCE;R0402;10kΩ ±1% 62.5mW 厚膜电阻;C25744;Resistors:Chip Resistor - Surface Mount;
+26;2;5.1kΩ;R3,R4;0402WGF5101TCE;R0402;5.1kΩ ±1% 62.5mW 厚膜电阻;C25905;Resistors:Chip Resistor - Surface Mount;
+27;1;100Ω;R17;0402WGF1000TCE;R0402;100Ω ±1% 62.5mW 厚膜电阻;C25076;Resistors:Chip Resistor - Surface Mount;
+28;1;475Ω;R18;RT0402BRD07475RL;R0402;薄膜电阻 475Ω ±0.1% 63mW;C852800;Resistors:Chip Resistor - Surface Mount;
+29;1;18GHz;RF1;733910083;SMA-TH_733910083;内孔 SMA 弯头;C493445;Connectors:Coaxial Connectors (RF);
+30;2;TS3425UA-3x4x2.5-160;SW1,SW2;TS3425UA-3x4x2.5-160;SW-SMD_4P-L4.2-W3.4_HX-TS3425PA-250GF-B;4.2mm*3.2mm 12V 50mA;C51927439;Switches:Tactile Switches;
+31;1;AP63203WU-7;U1;AP63203WU-7;TSOT-26_L2.9-W1.6-P0.95-LS2.8-BL;降压型 2A 3.8V~32V;C780769;Power Management (PMIC):DC-DC Converters;
+32;1;4.7uH;U2;BCIHP0420SC-4R7M;IND-SMD_L4.4-W4.2;4.7uH ±20% 3A;C2921168;Inductors, Coils, Chokes:Inductors (SMD);
+33;1;TPS7A2018PDBVR;U3;TPS7A2018PDBVR;TSOT-23-5_L2.9-W1.6-P0.95-LS2.8-BL;具有高 PSRR 的 300mA、超低噪声、低 IQ、低压降 (LDO) 线性稳压器;C963430;Power Management (PMIC):Voltage Regulators - Linear, Low Drop Out (LDO) Regulators;
+34;1;24AA025E48T-I/OT;U4;24AA025E48T-I/OT;SOT-23-6_L2.9-W1.6-P0.95-LS2.8-BR;带EUI-48或EUI-64节点标识的2K I2C串行EEPROM;C129895;Memory:EEPROM;EXACT MATCH
+35;1;SI4684-A10-GM;U6;SI4684-A10-GM;QFN-48_L7.0-W7.0-P0.50-TL-EP5.3;单芯片调频/数字音频广播/增强型数字音频广播收音机接收器;C1526088;RF and Wireless:RF Transceiver ICs;EXACT MATCH
+36;1;19.2MHz;U7;ABM8-19.200MHZ-10-1-U-T;CRYSTAL-SMD_4P-L3.2-W2.5-BL;19.2MHz ±10ppm 10pF;C1986852;Crystals, Oscillators, Resonators:Crystals;EXACT MATCH
+37;1;2.4GHz;U8;ESP32-S3-WROOM-1-N16;WIRELM-SMD_ESP32-S3-WROOM-1;不带固件 通用型Wi-Fi+低功耗蓝牙MCU模组;C2913199;IoT/Communication Modules:WiFi Modules;EXACT MATCH
+38;1;ADAU1701JSTZ-RL;U9;ADAU1701JSTZ-RL;LQFP-48_L7.0-W7.0-P0.50-LS9.0-TL;28-/56位音频处理器;C389590;Interface:Audio Interface ICs;EXACT MATCH
+40;1;TYPE-C-31-M-12;USBC1;TYPE-C-31-M-12;USB-C_SMD-TYPE-C-31-M-12_1;Type-C 母 卧贴;C165948;Connectors:USB Connectors;
+41;1;12.288MHz;X1;XTM32012288JT00351001;CRYSTAL-SMD_4P-L3.2-W2.5-BL;12.288MHz 4P 3225 12pF ±10ppm -20~70℃（±10ppm）;C41383238;Crystals, Oscillators, Resonators:Crystals;EXACT MATCH
@@ -334,10 +334,20 @@ the pin definitions in the source code must match it exactly.
 \section{Design validation and critical checks}
 \label{sec:hw-validation}

+A datasheet-level design review was performed in July~2026, before prototype
+fabrication, against \drpath{Hardware/DATASHEET/adau1701.pdf} and
+\drpath{Hardware/DATASHEET/SI4684-A10.pdf}. It found and corrected two
+defects on the schematic: \textbf{PLL\_MODE1} was tied to GND (which would
+have selected 64\,$\times$\,f\textsubscript{S} and run the ADAU1701 clock
+domain at 192\,kHz instead of 48\,kHz), and the Si4684 reference-crystal
+load capacitors were 12\,pF instead of the 15\,pF required for the
+10\,pF crystal (frequency pull, degraded RF). The board shipped with both
+fixes applied; the tables below record the \emph{as-fabricated} values.
+
 This section records the design-review checks performed against the
 component datasheets before fabrication, chip by chip. Items marked
 \emph{critical} can cause permanent damage or a non-functional board if
-violated, and were verified explicitly.
+violated, and were verified explicitly against the schematic.

 \subsection{Si4684 tuner}
 \label{sec:hw-val-si4684}
@@ -379,6 +389,9 @@ satisfying the +10\,\textmu s requirement in practice.
    VIO level              & 1.62--3.6\,V (3.3\,V to talk to ESP32)        & verified \\
    Bypass caps            & 2.2\,nF + 1\,\textmu F per VIO/VMEM/VCORE rail & verified \\
    SPI mode               & Mode 0 or 3, up to 10\,MHz, SMODE = GND       & verified \\
+    Reference crystal      & U7: 19.2\,MHz, CL = 10\,pF (XTALI/XTALO)     & verified \\
+    Crystal load caps      & C49/C50: 15\,pF C0G each (was 12\,pF in review) & verified \\
+    RSTB / INTB resistors  & 10\,k\(\Omega\) pull-down / 10\,k\(\Omega\) pull-up & verified \\
    SSB framing (firmware) & SSB held low for the whole transaction        & driver rule \\
    INTB                   & interrupt line, external pull-up (GPIO39)      & verified \\
    \bottomrule
@@ -396,6 +409,18 @@ Guide}. Boot and command protocol: AN649. Local copies:
 \drpath{Hardware/DATASHEET/} (see \drpath{README.md}).
 \end{drref}

+\begin{drnote}[Reference crystal and load capacitors]
+U7 is a 19.2\,MHz quartz (ABRACON ABM8-19.200MHZ-10-1-U-T) with
+\textbf{CL = 10\,pF} on XTALI (pin~15) and XTALO (pin~16). Load capacitors
+C49 and C50 are \textbf{15\,pF C0G/NP0} ($\pm$5\%) --- not X5R/X7R, which
+drift with temperature and bias. Quartz load caps must be C0G/NP0.
+
+Effective load: \(C_{L,\mathrm{eff}} = \frac{C_1 C_2}{C_1 + C_2} + C_{\mathrm{stray}}\).
+With 15\,pF caps the effective load is $\sim$9.5\,pF (correct for CL = 10\,pF).
+The original 12\,pF pair gave $\sim$8\,pF effective, pulling the oscillator
+high by roughly +10..25\,ppm and degrading tuner RF performance.
+\end{drnote}
+
 The core, memory, and analogue rails run at 1.8\,V; only VIO is at 3.3\,V
 to interface the ESP32. The 2.2\,nF and 1\,\textmu F bypass pairs are
 placed close to VIO (pin~34), VMEM (pin~35), and VCORE (pin~37) as AN851
@@ -414,19 +439,41 @@ loopback (MP10$\rightarrow$MP4, MP11$\rightarrow$MP5). Without it the DSP
 locks up when input data arrives.
 \end{drkey}

+\begin{drcaution}[PLL\_MODE strapping --- static, not GPIO]
+The ADAU1701 PLL multiplier is selected by \textbf{PLL\_MODE0} (pin~38) and
+\textbf{PLL\_MODE1} (pin~39). These are \emph{static straps} on the board;
+the ESP32 must never drive them. The datasheet requires both pins to be
+stable while RESET is held low, because the clock mode is latched as the
+device leaves reset.
+
+On the fabricated board: PLL\_MODE0 = GND; PLL\_MODE1 = 3V3 via R2
+(10\,k\(\Omega\)). This selects \textbf{256\,$\times$\,f\textsubscript{S}}:
+12.288\,MHz\,/\,256 = 48\,kHz.
+
+\textbf{Both pins tied to GND} selects 64\,$\times$\,f\textsubscript{S}
+(192\,kHz) and breaks the entire 48\,kHz I\textsuperscript{2}S clock domain
+--- the defect caught in the July~2026 review.
+\end{drcaution}
+
 \begin{table}[htbp]
  \centering
-  \small
-  \begin{tabular}{@{}L{2.2cm}L{3.6cm}L{7.2cm}@{}}
-    \drhead Check & Requirement (datasheet) & Status \\
+  \footnotesize
+  \begin{tabular}{@{}L{3.0cm}L{8.0cm}L{2.2cm}@{}}
+    \drhead Check & Requirement (datasheet / schematic) & Status \\
    \midrule
    Clock loopback   & MP10$\rightarrow$MP4, MP11$\rightarrow$MP5 wired     & verified \\
    Output master     & serial output port in Master Mode                   & verified \\
    MCLK ratio        & exactly 256\,$\times$\,f\textsubscript{S}           & verified \\
-    MCLK value        & 12.288\,MHz oscillator (256\,$\times$\,48\,kHz)      & verified \\
-    I\textsuperscript{2}C pull-ups & 2\,k\(\Omega\) on SDA/SCL (R16/R1)     & verified \\
+    MCLK source       & X1: 12.288\,MHz crystal (CL = 12\,pF); MCLKI/OSCO;
+      C41/C46 = 22\,pF; R17 = 100\,$\Omega$ on OSCO & verified \\
+    PLL\_MODE strapping & MODE0 = GND, MODE1 = 3V3 (256\,$\times$\,f\textsubscript{S}) & verified \\
+    I\textsuperscript{2}C pull-ups & 2\,k\(\Omega\) on SDA/SCL (R1/R16)     & verified \\
    I\textsuperscript{2}C address  & 0x34 (ADDR0 = ADDR1 = GND)               & verified \\
-    Self-boot         & disabled (host RAM load)                            & verified \\
+    VDRIVE (pin 17)   & tied to GND --- external 1.8\,V rail (TPS7A2018)   & verified \\
+    DVDD (pins 13, 24) & both on 1V8 rail                                & verified \\
+    SELFBOOT (pin 6)  & GND --- control-port mode, no self-boot             & verified \\
+    RSVD (pin 30)     & GND, as datasheet requires                        & verified \\
+    Self-boot policy  & disabled (host RAM load)                            & verified \\
    \bottomrule
  \end{tabular}
  \caption{ADAU1701 design checks. Reference: ADAU1701 data sheet (Rev.~C),
@@ -436,16 +483,35 @@ locks up when input data arrives.

 \begin{drref}[Datasheet]
 Master-clock loopback and serial-port modes:
-\texttt{Hardware/DATASHEET/adau1701.pdf}, Rev.~C, Table~63 and the serial-port
+\drpath{Hardware/DATASHEET/adau1701.pdf}, Rev.~C, Table~63 and the serial-port
 section. The master clock must be exactly 256\,$\times$\,f\textsubscript{S}.
-I\textsuperscript{2}C lines require pull-up resistors on SDA and SCL.
-DigiRadio uses \textbf{2\,k\(\Omega\)} (schematic R1/R16; ADAU1701 datasheet
+The 12.288\,MHz reference is a \textbf{passive crystal} (X1) between MCLKI
+(pin~32) and OSCO (pin~31) with 22\,pF load capacitors; the ADAU1701 uses its
+internal oscillator. I\textsuperscript{2}C lines require pull-up resistors on
+SDA and SCL. DigiRadio uses \textbf{2\,k\(\Omega\)} (schematic R1/R16; datasheet
 recommends 2.2\,k\(\Omega\) --- acceptable at 3.3\,V).
 \end{drref}

+\begin{drnote}[VDRIVE grounded]
+Pin~17 (VDRIVE) is tied to GND. The board provides an external 1.8\,V rail
+from the TPS7A2018, so the ADAU1701 internal regulator is unused. The
+datasheet allows VDRIVE to be tied to ground when an external DVDD supply is
+present.
+\end{drnote}
+
 \begin{drnote}[I\textsuperscript{2}C pull-ups confirmed]
 Schematic \texttt{DigitalRadio.pdf} and BOM list R1 (SCL) and R16 (SDA) as
-2\,k\(\Omega\) to 3V3 on the shared ADAU1701/EEPROM bus.
+2\,k\(\Omega\) to 3V3 on the shared ADAU1701/EEPROM bus (ESP32 sheet).
+\end{drnote}
+
+\begin{drnote}[CM and FILTD deviation --- analogue path unused]
+The ADAU1701 datasheet specifies 47\,\textmu F on CM (pin~40) and 10\,\textmu F
+on FILTD (pin~41). The fabricated board uses smaller values. This is
+acceptable because the audio chain is entirely digital (I\textsuperscript{2}S):
+ADC0/ADC1/ADC\_RES and VOUT0..VOUT3 are left floating, and the on-chip
+ADCs/DACs are powered down via the SigmaStudio ADC/power-control register.
+\textbf{Restore the datasheet capacitor values if the on-chip ADCs or DACs are
+ever used.}
 \end{drnote}

 \subsection{FSC-BT1035 (QCC3056)}
@@ -484,9 +550,9 @@ UART 115200/8/N/1, SSP on, auto-reconnect configurable via
  \begin{tabular}{@{}L{2.2cm}L{4.8cm}L{6.6cm}@{}}
    \drhead Area & Item & Status \\
    \midrule
-    Si4684 & RSTB pull-down, 1.8\,V rails, bypass caps, SPI & verified \\
-    Si4684 & RSTB release only in \texttt{Si4684Driver::boot()} & verified \\
-    ADAU1701 & clock loopback, master mode, 256$\times$f\textsubscript{S} & verified \\
+    Si4684 & RSTB/INTB 10\,k\(\Omega\) resistors, 19.2\,MHz crystal & verified \\
+    ADAU1701 & X1 crystal, PLL\_MODE 256$\times$f\textsubscript{S} & verified \\
+    ADAU1701 & clock loopback, master mode, VDRIVE/DVDD/SELFBOOT & verified \\
    ADAU1701 & I\textsuperscript{2}C 2\,k\(\Omega\) pull-ups (R1/R16) & verified \\
    FSC-BT1035 & UART + flow control, I\textsuperscript{2}S slave & verified \\
    Clocking & single 48\,kHz domain, ADAU master & verified \\
@@ -496,6 +562,7 @@ UART 115200/8/N/1, SSP on, auto-reconnect configurable via
  \label{tab:hw-val-summary}
 \end{table}

-The consolidated pre-fabrication validation is complete for all
-damage-class items (Si4684 power sequencing and supply levels) and the
-shared I\textsuperscript{2}C bus.
+The consolidated pre-fabrication validation is \textbf{complete}: every
+check in this section is closed against the as-fabricated schematic, including
+the July~2026 corrections to PLL\_MODE strapping and Si4684 crystal load
+capacitors. No hardware validation items remain open before fabrication.
@@ -32,9 +32,3 @@ Espressif, Feasycom/Qualcomm) whose datasheets, firmware images, and DSP
 tools remain subject to their respective vendors' terms. Those terms are
 unaffected by the DigiRadio licences and must be observed when
 redistributing vendor-supplied binaries.
-
-\begin{drnote}[Manufacturing partner]
-Prototype PCB fabrication and assembly are generously supported by
-\textbf{PCBWay}. See the acknowledgements on the back cover of this manual
-and the project repository for our thanks to their team.
-\end{drnote}
@@ -28,7 +28,10 @@ channel to compile; it is never used for a real download in this project.
 \label{sec:ss-hwcfg}

 The Hardware Configuration tab must mirror the board exactly. The key
-settings are collected in Table~\ref{tab:ss-hwcfg}.
+settings are collected in Table~\ref{tab:ss-hwcfg}. The 48\,kHz system
+sample rate follows from the \textbf{board strapping}, not from a
+SigmaStudio preference alone: X1 is a 12.288\,MHz crystal, PLL\_MODE selects
+256\,$\times$\,f\textsubscript{S}, and 12.288\,MHz\,/\,256 = 48\,kHz.

 \begin{table}[htbp]
  \centering
@@ -37,8 +40,8 @@ settings are collected in Table~\ref{tab:ss-hwcfg}.
    \midrule
    Control port (I\textsuperscript{2}C address) & 0x34 (ADDR0/ADDR1 = GND) \\
    Self-boot                     & Disabled (host RAM load) \\
-    System sample rate            & 48\,kHz \\
-    MCLK                          & 12.288\,MHz active oscillator \\
+    System sample rate            & 48\,kHz (256\,$\times$\,f\textsubscript{S} strapping) \\
+    MCLK                          & 12.288\,MHz crystal (256\,$\times$\,f\textsubscript{S}) \\
    Serial Input format           & I\textsuperscript{2}S, 24-bit \\
    Serial Output                 & \textbf{Master Mode} (ADAU generates clocks) \\
    Word length                   & 24 bits \\
@@ -49,6 +52,14 @@ settings are collected in Table~\ref{tab:ss-hwcfg}.
  \label{tab:ss-hwcfg}
 \end{table}

+\begin{drnote}[Clock source on the board]
+SigmaStudio's 48\,kHz sample-rate field must agree with the fabricated
+hardware: passive crystal X1 (12.288\,MHz, CL = 12\,pF) on MCLKI/OSCO with
+22\,pF load caps, PLL\_MODE0 = GND and PLL\_MODE1 = 3V3 (256\,$\times$\,f\textsubscript{S}).
+The ADAU1701 internal oscillator multiplies the crystal; it is not an active
+oscillator module. See Chapter~\ref{ch:hardware}, Section~\ref{sec:hw-val-adau}.
+\end{drnote}
+
 \subsection{Multipurpose pin (MP) assignment}

 The ADAU1701 multipurpose pins are assigned to the serial audio signals
@@ -186,8 +186,7 @@
 \newcommand{\drpath}[1]{\nolinkurl{#1}}
 % HTTP API subsection headings that wrap at slashes.
 \newcommand{\apiendpoint}[2]{%
-  \subsection{\texorpdfstring{%
-    {\raggedright\texttt{#1} \texttt{#2}\par}}{#1 #2}}%
+  \subsection{\texorpdfstring{\texttt{#1} \texttt{#2}}{#1 #2}}%
 }

 \endinput
@@ -35,11 +35,6 @@
 {\color{drGray}Hardware: CERN-OHL-S v2 \quad\textbullet\quad Firmware: Apache-2.0\par}
 \vspace{2mm}
 {\color{drGray}\small \url{https://github.com/manvalan/DigiRadio}\par}
-\vspace{1.2cm}
-{\color{drGray}\small
-Prototype PCB fabrication and assembly supported by
-\href{https://www.pcbway.com/}{\textcolor{drTeal}{\textbf{PCBWay}}}.
-\par}
 \end{titlepage}

 % ---------------- Contents ----------------
@@ -70,20 +65,15 @@ Prototype PCB fabrication and assembly supported by
 \begin{minipage}{0.82\textwidth}
 \centering
 {\color{drInk}
-This open-source hardware project was made possible with generous support from
-\textbf{PCBWay}, who sponsored prototype PCB fabrication and assembly for
-DigiRadio. Our sincere thanks and deep gratitude go to the PCBWay team for
-believing in the project and helping bring the first boards to life.\par}
+\textbf{PCBWay} sponsored part of the prototype PCB fabrication and assembly
+costs for DigiRadio. Their contribution did not cover the full production
+budget, but it materially reduced the out-of-pocket expense of the first
+manufacturing run. We thank the PCBWay team for believing in this open hardware
+project and for helping bring the first boards to life.\par}
 \vspace{1.2cm}
-\IfFileExists{figures/pcbway-logo.pdf}{%
-  \includegraphics[width=0.32\textwidth]{figures/pcbway-logo}%
+\includegraphics[width=0.32\textwidth]{figures/pcbway-logo.png}%
 \vspace{0.8cm}
 {\color{drGray}\small\url{https://www.pcbway.com}\par}
-}{%
-  {\color{drTeal}\Large\bfseries PCBWay\par}
-  \vspace{0.4cm}
-  {\color{drGray}\small\url{https://www.pcbway.com}\par}
-}
 \end{minipage}
 \end{center}
 \vspace*{\fill}
@@ -1,54 +0,0 @@
-# DigiRadio — repository documentation package
-
-Canonical layout for this repository:
-
-```
-DigiRadio/                          <- repo root (README, Hardware, LICENSE)
-├── CONTRIBUTING.md                 dev conventions (human-facing)
-├── README.md                       project overview (fw 0.8.3)
-└── Software/                       firmware project root (open THIS in Cursor)
-    ├── LICENSE                     Apache-2.0 (firmware)
-    ├── AGENTS.md                   authoritative coding rules
-    ├── instructions.md             agent kickoff + roadmap status
-    ├── sdkconfig.defaults          C++23, NVS + flash encryption (dev mode)
-    ├── sdkconfig.defaults.production  release-mode overlay (irreversible)
-    ├── partitions.csv              nvs + nvs_keys partitions
-    ├── Doxyfile                    API docs generation + enforcement
-    ├── apache-header.txt           header to paste in each source file
-    ├── .cursor/rules/*.mdc         Cursor scoped rules (6 files)
-    ├── tools/
-    │   ├── check-manual-sync.py    one LaTeX section per public class
-    │   ├── check_si4684_blobs.py   no proprietary .bin in git
-    │   ├── fetch_si4684_firmware.py  local blob procurement
-    │   └── gzip-www.sh             regenerate embedded web UI gzip
-    └── docs/
-        ├── TODO.md                 agent + HIL backlog
-        ├── security-flash-nvs.md   encryption + device checklist
-        └── manual/                 LaTeX technical manual (canonical)
-            ├── manual.tex
-            ├── ch-*.tex
-            └── manual.pdf          optional compiled preview
-```
-
-LaTeX sources live in `Software/docs/manual/`. Build the PDF from there:
-
-```bash
-cd Software/docs/manual && latexmk -lualatex manual.tex
-```
-
-## CI enforcement (from `Software/`)
-
-```bash
-doxygen Doxyfile
-python3 tools/check-manual-sync.py
-python3 tools/check_si4684_blobs.py
-```
-
-Host tests: `cmake -S components/core/test -B build-host && ctest --test-dir build-host`.
-
-## Notes
-
- Two LICENSE files: CERN-OHL-S at repo root (hardware), Apache-2.0 in
-  `Software/` (firmware).
- Si4684 `.bin` blobs are gitignored — never commit them.
- Open `Software/` as the Cursor project so rules and `AGENTS.md` load.