Add internet radio streaming with runtime API, modernize web UI, remove auto-tune/beep at boot
Streaming (main feature this session): - New WebRadioConfig/WebRadioJson core types, ISecureStore-backed persistence - New webradio::WebRadioService (thread-safe live config) + GET/POST /api/streaming - web_radio_stream task now runtime-toggleable (no reboot), no hardcoded URL - Content-Type diagnostic: warns clearly when a URL is a webpage, not an audio stream Boot cleanup: - Removed boot-time auto FM/DAB tune, auto-beep, and the (now-concluded) Si4684 crystal IBIAS/CTUN empirical sweep from main.cpp — tuning/beep are on-demand via the existing REST API only Web UI: - Modernized styling (cards, gradients, toggle switches, light/dark theme) - New Stream tab wired to /api/streaming Fixes found via real idf.py build (not just clangd): - Restored wrongly-removed si4684/Si4684Tuner.hpp include in main.cpp - Fixed MP3Decode() argument types in web_radio_stream.cpp (unsigned char**/int*) Quality-gate fixes: - Host-test stub headers (esp_log.h, freertos/*) so TunerService.cpp's scanForStation logging/pacing compiles for station_service_test / integration_service_test instead of running stale binaries - Added WifiScanner and WebRadioService manual sections; filled in missing Doxygen docs on BluetoothService, i2s_sdata_probe, test_firmware, Bt1035At - Ignore clangd's .cache/ index directory Also includes prior uncommitted work carried in the tree: Wi-Fi/Bluetooth device scan REST API and UI (WifiScanner, BT scan), SigmaStudio TCP bridge, and the current ADAU1701 SigmaStudio DSP program export. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Claude Sonnet 5
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/*
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* File: C:\Users\mikbi\Documents\Allegati\Desktop\DigiRadioTest\DigiRadio_IC_1_PARAM.h
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*
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* Created: Thursday, August 6, 2026 1:57:25 PM
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* Description: DigiRadio:IC 1 parameter RAM definitions.
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*
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* This software is distributed in the hope that it will be useful,
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* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* This software may only be used to program products purchased from
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* Analog Devices for incorporation by you into audio products that
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* are intended for resale to audio product end users. This software
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* may not be distributed whole or in any part to third parties.
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*
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* Copyright ©2026 Analog Devices, Inc. All rights reserved.
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*/
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#ifndef __DIGIRADIO_IC_1_PARAM_H__
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#define __DIGIRADIO_IC_1_PARAM_H__
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/* Module Beep1 - Beep Sources*/
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#define COUNT_BEEP1 3
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#define DEVICE_BEEP1 "IC1"
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#define ADDR_BEEP1_ENABLE 0
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#define FIXPT_BEEP1_ENABLE 0x00000000
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#define VALUE_BEEP1_ENABLE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_BEEP1_ENABLE SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_BEEP1_KICK 1
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#define FIXPT_BEEP1_KICK 0x00000000
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#define VALUE_BEEP1_KICK SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_BEEP1_KICK SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_BEEP1_BEEP_FREQ 2
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#define FIXPT_BEEP1_BEEP_FREQ 0x00006CAB
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#define VALUE_BEEP1_BEEP_FREQ SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.00331636677280911)
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#define TYPE_BEEP1_BEEP_FREQ SIGMASTUDIOTYPE_FIXPOINT
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/* Module Si4674 - Multiple Volume Control*/
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#define COUNT_SI4674 2
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#define DEVICE_SI4674 "IC1"
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#define ADDR_SI4674 3
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#define FIXPT_SI4674 0x00800000
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#define VALUE_SI4674 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_SI4674 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_SI4674_1 4
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#define FIXPT_SI4674_1 0x00800000
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#define VALUE_SI4674_1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_SI4674_1 SIGMASTUDIOTYPE_FIXPOINT
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/* Module ESP32 - Multiple Volume Control*/
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#define COUNT_ESP32 2
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#define DEVICE_ESP32 "IC1"
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#define ADDR_ESP32 5
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#define FIXPT_ESP32 0x00800000
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#define VALUE_ESP32 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_ESP32 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_ESP32_1 6
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#define FIXPT_ESP32_1 0x00800000
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#define VALUE_ESP32_1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_ESP32_1 SIGMASTUDIOTYPE_FIXPOINT
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/* Module St Mixer1 - Stereo Mixer*/
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#define COUNT_STMIXER1 2
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#define DEVICE_STMIXER1 "IC1"
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#define ADDR_STMIXER1_ST0_VOLUME 7
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#define FIXPT_STMIXER1_ST0_VOLUME 0x00800000
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#define VALUE_STMIXER1_ST0_VOLUME SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_STMIXER1_ST0_VOLUME SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_STMIXER1_ST1_VOLUME 8
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#define FIXPT_STMIXER1_ST1_VOLUME 0x00800000
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#define VALUE_STMIXER1_ST1_VOLUME SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_STMIXER1_ST1_VOLUME SIGMASTUDIOTYPE_FIXPOINT
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/* Module Param EQ1 - Parametric EQ*/
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#define COUNT_PARAMEQ1 60
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#define DEVICE_PARAMEQ1 "IC1"
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#define ADDR_PARAMEQ1_ST0_B0 9
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#define FIXPT_PARAMEQ1_ST0_B0 0x007FC365
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#define VALUE_PARAMEQ1_ST0_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.998150511190452)
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#define TYPE_PARAMEQ1_ST0_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_B0 9
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#define FIXPT_PARAMEQ1_ST0_B0 0x007FC365
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#define VALUE_PARAMEQ1_ST0_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.998150511190452)
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#define TYPE_PARAMEQ1_ST0_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_B1 10
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#define FIXPT_PARAMEQ1_ST0_B1 0xFF007936
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#define VALUE_PARAMEQ1_ST0_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-1.9963010223809)
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#define TYPE_PARAMEQ1_ST0_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_B1 10
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#define FIXPT_PARAMEQ1_ST0_B1 0xFF007936
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#define VALUE_PARAMEQ1_ST0_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-1.9963010223809)
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#define TYPE_PARAMEQ1_ST0_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_B2 11
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#define FIXPT_PARAMEQ1_ST0_B2 0x007FC365
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#define VALUE_PARAMEQ1_ST0_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.998150511190452)
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#define TYPE_PARAMEQ1_ST0_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_B2 11
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#define FIXPT_PARAMEQ1_ST0_B2 0x007FC365
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#define VALUE_PARAMEQ1_ST0_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.998150511190452)
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#define TYPE_PARAMEQ1_ST0_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_A0 12
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#define FIXPT_PARAMEQ1_ST0_A0 0x00FF86AE
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#define VALUE_PARAMEQ1_ST0_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.99629760176912)
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#define TYPE_PARAMEQ1_ST0_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_A0 12
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#define FIXPT_PARAMEQ1_ST0_A0 0x00FF86AE
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#define VALUE_PARAMEQ1_ST0_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.99629760176912)
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#define TYPE_PARAMEQ1_ST0_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_A1 13
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#define FIXPT_PARAMEQ1_ST0_A1 0xFF807919
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#define VALUE_PARAMEQ1_ST0_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.996304442992686)
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#define TYPE_PARAMEQ1_ST0_A1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST0_A1 13
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#define FIXPT_PARAMEQ1_ST0_A1 0xFF807919
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#define VALUE_PARAMEQ1_ST0_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.996304442992686)
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#define TYPE_PARAMEQ1_ST0_A1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_B0 14
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#define FIXPT_PARAMEQ1_ST1_B0 0x00800000
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#define VALUE_PARAMEQ1_ST1_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_PARAMEQ1_ST1_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_B0 14
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#define FIXPT_PARAMEQ1_ST1_B0 0x00800000
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#define VALUE_PARAMEQ1_ST1_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_PARAMEQ1_ST1_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_B1 15
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#define FIXPT_PARAMEQ1_ST1_B1 0x00000000
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#define VALUE_PARAMEQ1_ST1_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_B1 15
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#define FIXPT_PARAMEQ1_ST1_B1 0x00000000
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#define VALUE_PARAMEQ1_ST1_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_B2 16
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#define FIXPT_PARAMEQ1_ST1_B2 0x00000000
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#define VALUE_PARAMEQ1_ST1_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_B2 16
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#define FIXPT_PARAMEQ1_ST1_B2 0x00000000
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#define VALUE_PARAMEQ1_ST1_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_A0 17
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#define FIXPT_PARAMEQ1_ST1_A0 0x00000000
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#define VALUE_PARAMEQ1_ST1_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_A0 17
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#define FIXPT_PARAMEQ1_ST1_A0 0x00000000
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#define VALUE_PARAMEQ1_ST1_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_A1 18
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#define FIXPT_PARAMEQ1_ST1_A1 0x00000000
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#define VALUE_PARAMEQ1_ST1_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_A1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST1_A1 18
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#define FIXPT_PARAMEQ1_ST1_A1 0x00000000
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#define VALUE_PARAMEQ1_ST1_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST1_A1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_B0 19
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#define FIXPT_PARAMEQ1_ST2_B0 0x00800000
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#define VALUE_PARAMEQ1_ST2_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_PARAMEQ1_ST2_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_B0 19
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#define FIXPT_PARAMEQ1_ST2_B0 0x00800000
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#define VALUE_PARAMEQ1_ST2_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_PARAMEQ1_ST2_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_B1 20
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#define FIXPT_PARAMEQ1_ST2_B1 0x00000000
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#define VALUE_PARAMEQ1_ST2_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_B1 20
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#define FIXPT_PARAMEQ1_ST2_B1 0x00000000
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#define VALUE_PARAMEQ1_ST2_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_B2 21
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#define FIXPT_PARAMEQ1_ST2_B2 0x00000000
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#define VALUE_PARAMEQ1_ST2_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_B2 21
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#define FIXPT_PARAMEQ1_ST2_B2 0x00000000
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#define VALUE_PARAMEQ1_ST2_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_A0 22
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#define FIXPT_PARAMEQ1_ST2_A0 0x00000000
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#define VALUE_PARAMEQ1_ST2_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_A0 22
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#define FIXPT_PARAMEQ1_ST2_A0 0x00000000
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#define VALUE_PARAMEQ1_ST2_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_A1 23
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#define FIXPT_PARAMEQ1_ST2_A1 0x00000000
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#define VALUE_PARAMEQ1_ST2_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_A1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST2_A1 23
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#define FIXPT_PARAMEQ1_ST2_A1 0x00000000
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#define VALUE_PARAMEQ1_ST2_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST2_A1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_B0 24
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#define FIXPT_PARAMEQ1_ST3_B0 0x00800000
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#define VALUE_PARAMEQ1_ST3_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_PARAMEQ1_ST3_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_B0 24
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#define FIXPT_PARAMEQ1_ST3_B0 0x00800000
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#define VALUE_PARAMEQ1_ST3_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
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#define TYPE_PARAMEQ1_ST3_B0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_B1 25
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#define FIXPT_PARAMEQ1_ST3_B1 0x00000000
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#define VALUE_PARAMEQ1_ST3_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST3_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_B1 25
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#define FIXPT_PARAMEQ1_ST3_B1 0x00000000
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#define VALUE_PARAMEQ1_ST3_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST3_B1 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_B2 26
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#define FIXPT_PARAMEQ1_ST3_B2 0x00000000
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#define VALUE_PARAMEQ1_ST3_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST3_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_B2 26
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#define FIXPT_PARAMEQ1_ST3_B2 0x00000000
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#define VALUE_PARAMEQ1_ST3_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST3_B2 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_A0 27
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#define FIXPT_PARAMEQ1_ST3_A0 0x00000000
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#define VALUE_PARAMEQ1_ST3_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST3_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_A0 27
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#define FIXPT_PARAMEQ1_ST3_A0 0x00000000
|
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#define VALUE_PARAMEQ1_ST3_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
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#define TYPE_PARAMEQ1_ST3_A0 SIGMASTUDIOTYPE_FIXPOINT
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#define ADDR_PARAMEQ1_ST3_A1 28
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#define FIXPT_PARAMEQ1_ST3_A1 0x00000000
|
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#define VALUE_PARAMEQ1_ST3_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
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#define TYPE_PARAMEQ1_ST3_A1 SIGMASTUDIOTYPE_FIXPOINT
|
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#define ADDR_PARAMEQ1_ST3_A1 28
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#define FIXPT_PARAMEQ1_ST3_A1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST3_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST3_A1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_B0 29
|
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#define FIXPT_PARAMEQ1_ST4_B0 0x00800000
|
||||
#define VALUE_PARAMEQ1_ST4_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_PARAMEQ1_ST4_B0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_B0 29
|
||||
#define FIXPT_PARAMEQ1_ST4_B0 0x00800000
|
||||
#define VALUE_PARAMEQ1_ST4_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_PARAMEQ1_ST4_B0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_B1 30
|
||||
#define FIXPT_PARAMEQ1_ST4_B1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_B1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_B1 30
|
||||
#define FIXPT_PARAMEQ1_ST4_B1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_B1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_B2 31
|
||||
#define FIXPT_PARAMEQ1_ST4_B2 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_B2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_B2 31
|
||||
#define FIXPT_PARAMEQ1_ST4_B2 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_B2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_A0 32
|
||||
#define FIXPT_PARAMEQ1_ST4_A0 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_A0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_A0 32
|
||||
#define FIXPT_PARAMEQ1_ST4_A0 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_A0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_A1 33
|
||||
#define FIXPT_PARAMEQ1_ST4_A1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_A1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST4_A1 33
|
||||
#define FIXPT_PARAMEQ1_ST4_A1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST4_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST4_A1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_B0 34
|
||||
#define FIXPT_PARAMEQ1_ST5_B0 0x00800000
|
||||
#define VALUE_PARAMEQ1_ST5_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_PARAMEQ1_ST5_B0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_B0 34
|
||||
#define FIXPT_PARAMEQ1_ST5_B0 0x00800000
|
||||
#define VALUE_PARAMEQ1_ST5_B0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_PARAMEQ1_ST5_B0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_B1 35
|
||||
#define FIXPT_PARAMEQ1_ST5_B1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_B1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_B1 35
|
||||
#define FIXPT_PARAMEQ1_ST5_B1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_B1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_B1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_B2 36
|
||||
#define FIXPT_PARAMEQ1_ST5_B2 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_B2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_B2 36
|
||||
#define FIXPT_PARAMEQ1_ST5_B2 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_B2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_B2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_A0 37
|
||||
#define FIXPT_PARAMEQ1_ST5_A0 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_A0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_A0 37
|
||||
#define FIXPT_PARAMEQ1_ST5_A0 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_A0 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_A0 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_A1 38
|
||||
#define FIXPT_PARAMEQ1_ST5_A1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_A1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_PARAMEQ1_ST5_A1 38
|
||||
#define FIXPT_PARAMEQ1_ST5_A1 0x00000000
|
||||
#define VALUE_PARAMEQ1_ST5_A1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)
|
||||
#define TYPE_PARAMEQ1_ST5_A1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Multiple 1 - Multiple Volume Control*/
|
||||
#define COUNT_MULTIPLE1 2
|
||||
#define DEVICE_MULTIPLE1 "IC1"
|
||||
#define ADDR_MULTIPLE1 39
|
||||
#define FIXPT_MULTIPLE1 0x00800000
|
||||
#define VALUE_MULTIPLE1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_MULTIPLE1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_MULTIPLE1_1 40
|
||||
#define FIXPT_MULTIPLE1_1 0x00800000
|
||||
#define VALUE_MULTIPLE1_1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_MULTIPLE1_1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Limiter 1 - Limiter*/
|
||||
#define COUNT_LIMITER1 15
|
||||
#define DEVICE_LIMITER1 "IC1"
|
||||
#define ADDR_LIMITER1_S1 41
|
||||
#define FIXPT_LIMITER1_S1 0xFFFE2BE3
|
||||
#define VALUE_LIMITER1_S1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.01428571428571)
|
||||
#define TYPE_LIMITER1_S1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_INT1 42
|
||||
#define FIXPT_LIMITER1_INT1 0x0022BE2B
|
||||
#define VALUE_LIMITER1_INT1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.27142857142857)
|
||||
#define TYPE_LIMITER1_INT1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_S2 43
|
||||
#define FIXPT_LIMITER1_S2 0xFFEAAAAB
|
||||
#define VALUE_LIMITER1_S2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.16666666666667)
|
||||
#define TYPE_LIMITER1_S2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_INT2 44
|
||||
#define FIXPT_LIMITER1_INT2 0x006AAAAA
|
||||
#define VALUE_LIMITER1_INT2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.8333333333333)
|
||||
#define TYPE_LIMITER1_INT2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_S3 45
|
||||
#define FIXPT_LIMITER1_S3 0xFF9A69A7
|
||||
#define VALUE_LIMITER1_S3 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.79365079365079)
|
||||
#define TYPE_LIMITER1_S3 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_INT3 46
|
||||
#define FIXPT_LIMITER1_INT3 0x00FDF7DF
|
||||
#define VALUE_LIMITER1_INT3 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.98412698412698)
|
||||
#define TYPE_LIMITER1_INT3 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_S4 47
|
||||
#define FIXPT_LIMITER1_S4 0xF83C6C20
|
||||
#define VALUE_LIMITER1_S4 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-15.527950310559)
|
||||
#define TYPE_LIMITER1_S4 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_INT4 48
|
||||
#define FIXPT_LIMITER1_INT4 0x03F5AA22
|
||||
#define VALUE_LIMITER1_INT4 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(7.91925465838509)
|
||||
#define TYPE_LIMITER1_INT4 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_C1 49
|
||||
#define FIXPT_LIMITER1_C1 0x01800000
|
||||
#define VALUE_LIMITER1_C1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(3)
|
||||
#define TYPE_LIMITER1_C1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_C2 50
|
||||
#define FIXPT_LIMITER1_C2 0x01000000
|
||||
#define VALUE_LIMITER1_C2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(2)
|
||||
#define TYPE_LIMITER1_C2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_C3 51
|
||||
#define FIXPT_LIMITER1_C3 0x00333333
|
||||
#define VALUE_LIMITER1_C3 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.4)
|
||||
#define TYPE_LIMITER1_C3 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_THRESHOLD 52
|
||||
#define FIXPT_LIMITER1_THRESHOLD 0x00800000
|
||||
#define VALUE_LIMITER1_THRESHOLD SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_LIMITER1_THRESHOLD SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_RMS 53
|
||||
#define FIXPT_LIMITER1_RMS 0x000007DC
|
||||
#define VALUE_LIMITER1_RMS SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000239881380791562)
|
||||
#define TYPE_LIMITER1_RMS SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_DECAY 54
|
||||
#define FIXPT_LIMITER1_DECAY 0x00000800
|
||||
#define VALUE_LIMITER1_DECAY SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000244140625)
|
||||
#define TYPE_LIMITER1_DECAY SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER1_DECAYCOMPLEMENT 55
|
||||
#define FIXPT_LIMITER1_DECAYCOMPLEMENT 0x007FF000
|
||||
#define VALUE_LIMITER1_DECAYCOMPLEMENT SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.99951171875)
|
||||
#define TYPE_LIMITER1_DECAYCOMPLEMENT SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Limiter 2 - Limiter*/
|
||||
#define COUNT_LIMITER2 15
|
||||
#define DEVICE_LIMITER2 "IC1"
|
||||
#define ADDR_LIMITER2_S1 56
|
||||
#define FIXPT_LIMITER2_S1 0xFFFE2BE3
|
||||
#define VALUE_LIMITER2_S1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.01428571428571)
|
||||
#define TYPE_LIMITER2_S1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_INT1 57
|
||||
#define FIXPT_LIMITER2_INT1 0x0022BE2B
|
||||
#define VALUE_LIMITER2_INT1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.27142857142857)
|
||||
#define TYPE_LIMITER2_INT1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_S2 58
|
||||
#define FIXPT_LIMITER2_S2 0xFFEAAAAB
|
||||
#define VALUE_LIMITER2_S2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.16666666666667)
|
||||
#define TYPE_LIMITER2_S2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_INT2 59
|
||||
#define FIXPT_LIMITER2_INT2 0x006AAAAA
|
||||
#define VALUE_LIMITER2_INT2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.8333333333333)
|
||||
#define TYPE_LIMITER2_INT2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_S3 60
|
||||
#define FIXPT_LIMITER2_S3 0xFF9A69A7
|
||||
#define VALUE_LIMITER2_S3 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.79365079365079)
|
||||
#define TYPE_LIMITER2_S3 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_INT3 61
|
||||
#define FIXPT_LIMITER2_INT3 0x00FDF7DF
|
||||
#define VALUE_LIMITER2_INT3 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.98412698412698)
|
||||
#define TYPE_LIMITER2_INT3 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_S4 62
|
||||
#define FIXPT_LIMITER2_S4 0xF83C6C20
|
||||
#define VALUE_LIMITER2_S4 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-15.527950310559)
|
||||
#define TYPE_LIMITER2_S4 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_INT4 63
|
||||
#define FIXPT_LIMITER2_INT4 0x03F5AA22
|
||||
#define VALUE_LIMITER2_INT4 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(7.91925465838509)
|
||||
#define TYPE_LIMITER2_INT4 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_C1 64
|
||||
#define FIXPT_LIMITER2_C1 0x01800000
|
||||
#define VALUE_LIMITER2_C1 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(3)
|
||||
#define TYPE_LIMITER2_C1 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_C2 65
|
||||
#define FIXPT_LIMITER2_C2 0x01000000
|
||||
#define VALUE_LIMITER2_C2 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(2)
|
||||
#define TYPE_LIMITER2_C2 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_C3 66
|
||||
#define FIXPT_LIMITER2_C3 0x00333333
|
||||
#define VALUE_LIMITER2_C3 SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.4)
|
||||
#define TYPE_LIMITER2_C3 SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_THRESHOLD 67
|
||||
#define FIXPT_LIMITER2_THRESHOLD 0x00800000
|
||||
#define VALUE_LIMITER2_THRESHOLD SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define TYPE_LIMITER2_THRESHOLD SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_RMS 68
|
||||
#define FIXPT_LIMITER2_RMS 0x000007DC
|
||||
#define VALUE_LIMITER2_RMS SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000239881380791562)
|
||||
#define TYPE_LIMITER2_RMS SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_DECAY 69
|
||||
#define FIXPT_LIMITER2_DECAY 0x00000800
|
||||
#define VALUE_LIMITER2_DECAY SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000244140625)
|
||||
#define TYPE_LIMITER2_DECAY SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define ADDR_LIMITER2_DECAYCOMPLEMENT 70
|
||||
#define FIXPT_LIMITER2_DECAYCOMPLEMENT 0x007FF000
|
||||
#define VALUE_LIMITER2_DECAYCOMPLEMENT SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.99951171875)
|
||||
#define TYPE_LIMITER2_DECAYCOMPLEMENT SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,565 @@
|
||||
/*
|
||||
* File: C:\Users\mikbi\Documents\Allegati\Desktop\DigiRadioTest\DigiRadio_IC_1_REG.h
|
||||
*
|
||||
* Created: Thursday, August 6, 2026 1:57:25 PM
|
||||
* Description: DigiRadio:IC 1 control register definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2026 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __DIGIRADIO_IC_1_REG_H__
|
||||
#define __DIGIRADIO_IC_1_REG_H__
|
||||
|
||||
|
||||
/* InterfaceRegister0 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER0_IC_1_ADDR 0x800
|
||||
#define REG_INTERFACEREGISTER0_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER0_IC_1_VALUE 0x0
|
||||
|
||||
/* InterfaceRegister1 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER1_IC_1_ADDR 0x801
|
||||
#define REG_INTERFACEREGISTER1_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER1_IC_1_VALUE 0x0
|
||||
|
||||
/* InterfaceRegister2 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER2_IC_1_ADDR 0x802
|
||||
#define REG_INTERFACEREGISTER2_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER2_IC_1_VALUE 0x0
|
||||
|
||||
/* InterfaceRegister3 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER3_IC_1_ADDR 0x803
|
||||
#define REG_INTERFACEREGISTER3_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER3_IC_1_VALUE 0x0
|
||||
|
||||
/* InterfaceRegister4 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER4_IC_1_ADDR 0x804
|
||||
#define REG_INTERFACEREGISTER4_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER4_IC_1_VALUE 0x0
|
||||
|
||||
/* InterfaceRegister5 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER5_IC_1_ADDR 0x805
|
||||
#define REG_INTERFACEREGISTER5_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER5_IC_1_VALUE 0x0
|
||||
|
||||
/* InterfaceRegister6 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER6_IC_1_ADDR 0x806
|
||||
#define REG_INTERFACEREGISTER6_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER6_IC_1_VALUE 0x0
|
||||
|
||||
/* InterfaceRegister7 - Registers (IC 1) */
|
||||
#define REG_INTERFACEREGISTER7_IC_1_ADDR 0x807
|
||||
#define REG_INTERFACEREGISTER7_IC_1_BYTE 4
|
||||
#define REG_INTERFACEREGISTER7_IC_1_VALUE 0x0
|
||||
|
||||
/* GpioAllRegister - Registers (IC 1) */
|
||||
#define REG_GPIOALLREGISTER_IC_1_ADDR 0x808
|
||||
#define REG_GPIOALLREGISTER_IC_1_BYTE 2
|
||||
#define REG_GPIOALLREGISTER_IC_1_VALUE 0x0
|
||||
|
||||
/* Adc0 - Registers (IC 1) */
|
||||
#define REG_ADC0_IC_1_ADDR 0x809
|
||||
#define REG_ADC0_IC_1_BYTE 1
|
||||
#define REG_ADC0_IC_1_VALUE 0x0
|
||||
|
||||
/* Adc1 - Registers (IC 1) */
|
||||
#define REG_ADC1_IC_1_ADDR 0x80A
|
||||
#define REG_ADC1_IC_1_BYTE 1
|
||||
#define REG_ADC1_IC_1_VALUE 0x0
|
||||
|
||||
/* Adc2 - Registers (IC 1) */
|
||||
#define REG_ADC2_IC_1_ADDR 0x80B
|
||||
#define REG_ADC2_IC_1_BYTE 1
|
||||
#define REG_ADC2_IC_1_VALUE 0x0
|
||||
|
||||
/* Adc3 - Registers (IC 1) */
|
||||
#define REG_ADC3_IC_1_ADDR 0x80C
|
||||
#define REG_ADC3_IC_1_BYTE 1
|
||||
#define REG_ADC3_IC_1_VALUE 0x0
|
||||
|
||||
/* CoreRegister - Registers (IC 1) */
|
||||
#define REG_COREREGISTER_IC_1_ADDR 0x81C
|
||||
#define REG_COREREGISTER_IC_1_BYTE 2
|
||||
#define REG_COREREGISTER_IC_1_VALUE 0x1C
|
||||
|
||||
/* RAMRegister - Registers (IC 1) */
|
||||
#define REG_RAMREGISTER_IC_1_ADDR 0x81D
|
||||
#define REG_RAMREGISTER_IC_1_BYTE 1
|
||||
#define REG_RAMREGISTER_IC_1_VALUE 0x8
|
||||
|
||||
/* SerialOutRegister1 - Registers (IC 1) */
|
||||
#define REG_SERIALOUTREGISTER1_IC_1_ADDR 0x81E
|
||||
#define REG_SERIALOUTREGISTER1_IC_1_BYTE 2
|
||||
#define REG_SERIALOUTREGISTER1_IC_1_VALUE 0x800
|
||||
|
||||
/* SerialInputRegister - Registers (IC 1) */
|
||||
#define REG_SERIALINPUTREGISTER_IC_1_ADDR 0x81F
|
||||
#define REG_SERIALINPUTREGISTER_IC_1_BYTE 1
|
||||
#define REG_SERIALINPUTREGISTER_IC_1_VALUE 0x0
|
||||
|
||||
/* MpCfg0 - Registers (IC 1) */
|
||||
#define REG_MPCFG0_IC_1_ADDR 0x820
|
||||
#define REG_MPCFG0_IC_1_BYTE 3
|
||||
#define REG_MPCFG0_IC_1_VALUE 0x440044
|
||||
|
||||
/* MpCfg1 - Registers (IC 1) */
|
||||
#define REG_MPCFG1_IC_1_ADDR 0x821
|
||||
#define REG_MPCFG1_IC_1_BYTE 3
|
||||
#define REG_MPCFG1_IC_1_VALUE 0x440004
|
||||
|
||||
/* AnalogPowerDownRegister - Registers (IC 1) */
|
||||
#define REG_ANALOGPOWERDOWNREGISTER_IC_1_ADDR 0x822
|
||||
#define REG_ANALOGPOWERDOWNREGISTER_IC_1_BYTE 2
|
||||
#define REG_ANALOGPOWERDOWNREGISTER_IC_1_VALUE 0x0
|
||||
|
||||
/* TestRegister - Registers (IC 1) */
|
||||
#define REG_TESTREGISTER_IC_1_ADDR 0x823
|
||||
#define REG_TESTREGISTER_IC_1_BYTE 2
|
||||
#define REG_TESTREGISTER_IC_1_VALUE 0x0
|
||||
|
||||
/* AnalogInterfaceRegister0 - Registers (IC 1) */
|
||||
#define REG_ANALOGINTERFACEREGISTER0_IC_1_ADDR 0x824
|
||||
#define REG_ANALOGINTERFACEREGISTER0_IC_1_BYTE 2
|
||||
#define REG_ANALOGINTERFACEREGISTER0_IC_1_VALUE 0x8000
|
||||
|
||||
/* AnalogInterfaceRegister1 - Registers (IC 1) */
|
||||
#define REG_ANALOGINTERFACEREGISTER1_IC_1_ADDR 0x825
|
||||
#define REG_ANALOGINTERFACEREGISTER1_IC_1_BYTE 2
|
||||
#define REG_ANALOGINTERFACEREGISTER1_IC_1_VALUE 0x0
|
||||
|
||||
/* AnalogInterfaceRegister2 - Registers (IC 1) */
|
||||
#define REG_ANALOGINTERFACEREGISTER2_IC_1_ADDR 0x826
|
||||
#define REG_ANALOGINTERFACEREGISTER2_IC_1_BYTE 2
|
||||
#define REG_ANALOGINTERFACEREGISTER2_IC_1_VALUE 0x0
|
||||
|
||||
/* AnalogInterfaceRegister3 - Registers (IC 1) */
|
||||
#define REG_ANALOGINTERFACEREGISTER3_IC_1_ADDR 0x827
|
||||
#define REG_ANALOGINTERFACEREGISTER3_IC_1_BYTE 2
|
||||
#define REG_ANALOGINTERFACEREGISTER3_IC_1_VALUE 0x1
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* Control register's field descriptions
|
||||
*
|
||||
*/
|
||||
|
||||
/* InterfaceRegister0 (IC 1) */
|
||||
#define R0_INTERFACEREGISTER0_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R0_INTERFACEREGISTER0_IC_1_MASK 0xFFFFFFFF
|
||||
#define R0_INTERFACEREGISTER0_IC_1_SHIFT 0
|
||||
|
||||
/* InterfaceRegister1 (IC 1) */
|
||||
#define R1_INTERFACEREGISTER1_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R1_INTERFACEREGISTER1_IC_1_MASK 0xFFFFFFFF
|
||||
#define R1_INTERFACEREGISTER1_IC_1_SHIFT 0
|
||||
|
||||
/* InterfaceRegister2 (IC 1) */
|
||||
#define R2_INTERFACEREGISTER2_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R2_INTERFACEREGISTER2_IC_1_MASK 0xFFFFFFFF
|
||||
#define R2_INTERFACEREGISTER2_IC_1_SHIFT 0
|
||||
|
||||
/* InterfaceRegister3 (IC 1) */
|
||||
#define R3_INTERFACEREGISTER3_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R3_INTERFACEREGISTER3_IC_1_MASK 0xFFFFFFFF
|
||||
#define R3_INTERFACEREGISTER3_IC_1_SHIFT 0
|
||||
|
||||
/* InterfaceRegister4 (IC 1) */
|
||||
#define R4_INTERFACEREGISTER4_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R4_INTERFACEREGISTER4_IC_1_MASK 0xFFFFFFFF
|
||||
#define R4_INTERFACEREGISTER4_IC_1_SHIFT 0
|
||||
|
||||
/* InterfaceRegister5 (IC 1) */
|
||||
#define R5_INTERFACEREGISTER5_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R5_INTERFACEREGISTER5_IC_1_MASK 0xFFFFFFFF
|
||||
#define R5_INTERFACEREGISTER5_IC_1_SHIFT 0
|
||||
|
||||
/* InterfaceRegister6 (IC 1) */
|
||||
#define R6_INTERFACEREGISTER6_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R6_INTERFACEREGISTER6_IC_1_MASK 0xFFFFFFFF
|
||||
#define R6_INTERFACEREGISTER6_IC_1_SHIFT 0
|
||||
|
||||
/* InterfaceRegister7 (IC 1) */
|
||||
#define R7_INTERFACEREGISTER7_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
|
||||
#define R7_INTERFACEREGISTER7_IC_1_MASK 0xFFFFFFFF
|
||||
#define R7_INTERFACEREGISTER7_IC_1_SHIFT 0
|
||||
|
||||
/* GpioAllRegister (IC 1) */
|
||||
#define R8_PIN0_IC_1 0x0 /* 0b [0] */
|
||||
#define R8_PIN1_IC_1 0x0 /* 0b [1] */
|
||||
#define R8_PIN2_IC_1 0x0 /* 0b [2] */
|
||||
#define R8_PIN3_IC_1 0x0 /* 0b [3] */
|
||||
#define R8_PIN4_IC_1 0x0 /* 0b [4] */
|
||||
#define R8_PIN5_IC_1 0x0 /* 0b [5] */
|
||||
#define R8_PIN6_IC_1 0x0 /* 0b [6] */
|
||||
#define R8_PIN7_IC_1 0x0 /* 0b [7] */
|
||||
#define R8_PIN8_IC_1 0x0 /* 0b [8] */
|
||||
#define R8_PIN9_IC_1 0x0 /* 0b [9] */
|
||||
#define R8_PIN10_IC_1 0x0 /* 0b [10] */
|
||||
#define R8_PIN11_IC_1 0x0 /* 0b [11] */
|
||||
#define R8_PIN0_IC_1_MASK 0x1
|
||||
#define R8_PIN0_IC_1_SHIFT 0
|
||||
#define R8_PIN1_IC_1_MASK 0x2
|
||||
#define R8_PIN1_IC_1_SHIFT 1
|
||||
#define R8_PIN2_IC_1_MASK 0x4
|
||||
#define R8_PIN2_IC_1_SHIFT 2
|
||||
#define R8_PIN3_IC_1_MASK 0x8
|
||||
#define R8_PIN3_IC_1_SHIFT 3
|
||||
#define R8_PIN4_IC_1_MASK 0x10
|
||||
#define R8_PIN4_IC_1_SHIFT 4
|
||||
#define R8_PIN5_IC_1_MASK 0x20
|
||||
#define R8_PIN5_IC_1_SHIFT 5
|
||||
#define R8_PIN6_IC_1_MASK 0x40
|
||||
#define R8_PIN6_IC_1_SHIFT 6
|
||||
#define R8_PIN7_IC_1_MASK 0x80
|
||||
#define R8_PIN7_IC_1_SHIFT 7
|
||||
#define R8_PIN8_IC_1_MASK 0x100
|
||||
#define R8_PIN8_IC_1_SHIFT 8
|
||||
#define R8_PIN9_IC_1_MASK 0x200
|
||||
#define R8_PIN9_IC_1_SHIFT 9
|
||||
#define R8_PIN10_IC_1_MASK 0x400
|
||||
#define R8_PIN10_IC_1_SHIFT 10
|
||||
#define R8_PIN11_IC_1_MASK 0x800
|
||||
#define R8_PIN11_IC_1_SHIFT 11
|
||||
|
||||
/* Adc0 (IC 1) */
|
||||
#define R9_ADC0_IC_1 0x00 /* 00000000b [7:0] */
|
||||
#define R9_ADC0_IC_1_MASK 0xFF
|
||||
#define R9_ADC0_IC_1_SHIFT 0
|
||||
|
||||
/* Adc1 (IC 1) */
|
||||
#define R10_ADC1_IC_1 0x00 /* 00000000b [7:0] */
|
||||
#define R10_ADC1_IC_1_MASK 0xFF
|
||||
#define R10_ADC1_IC_1_SHIFT 0
|
||||
|
||||
/* Adc2 (IC 1) */
|
||||
#define R11_ADC2_IC_1 0x00 /* 00000000b [7:0] */
|
||||
#define R11_ADC2_IC_1_MASK 0xFF
|
||||
#define R11_ADC2_IC_1_SHIFT 0
|
||||
|
||||
/* Adc3 (IC 1) */
|
||||
#define R12_ADC3_IC_1 0x00 /* 00000000b [7:0] */
|
||||
#define R12_ADC3_IC_1_MASK 0xFF
|
||||
#define R12_ADC3_IC_1_SHIFT 0
|
||||
|
||||
/* CoreRegister (IC 1) */
|
||||
#define R13_PROGRAM_LENGTH_IC_1 0x0 /* 00b [1:0] */
|
||||
#define R13_REGISTER_ZERO_IC_1 0x1 /* 1b [2] */
|
||||
#define R13_MUTE_DAC_IC_1 0x1 /* 1b [3] */
|
||||
#define R13_MUTE_ADC_IC_1 0x1 /* 1b [4] */
|
||||
#define R13_SAFELOAD_IC_1 0x0 /* 0b [5] */
|
||||
#define R13_WRITESPI_INTERFACEREG_IC_1 0x0 /* 0b [6] */
|
||||
#define R13_WRITESPI_GPIO_IC_1 0x0 /* 0b [7] */
|
||||
#define R13_WRITESPI_ADC_IC_1 0x0 /* 0b [8] */
|
||||
#define R13_MUTE_SERIALIN_IC_1 0x0 /* 0b [9] */
|
||||
#define R13_GPIO_DEBOUNCE_IC_1 0x0 /* 00b [11:10] */
|
||||
#define R13_EXTMEM_SPEED_IC_1 0x0 /* 00b [13:12] */
|
||||
#define R13_PROGRAM_LENGTH_IC_1_MASK 0x3
|
||||
#define R13_PROGRAM_LENGTH_IC_1_SHIFT 0
|
||||
#define R13_REGISTER_ZERO_IC_1_MASK 0x4
|
||||
#define R13_REGISTER_ZERO_IC_1_SHIFT 2
|
||||
#define R13_MUTE_DAC_IC_1_MASK 0x8
|
||||
#define R13_MUTE_DAC_IC_1_SHIFT 3
|
||||
#define R13_MUTE_ADC_IC_1_MASK 0x10
|
||||
#define R13_MUTE_ADC_IC_1_SHIFT 4
|
||||
#define R13_SAFELOAD_IC_1_MASK 0x20
|
||||
#define R13_SAFELOAD_IC_1_SHIFT 5
|
||||
#define R13_WRITESPI_INTERFACEREG_IC_1_MASK 0x40
|
||||
#define R13_WRITESPI_INTERFACEREG_IC_1_SHIFT 6
|
||||
#define R13_WRITESPI_GPIO_IC_1_MASK 0x80
|
||||
#define R13_WRITESPI_GPIO_IC_1_SHIFT 7
|
||||
#define R13_WRITESPI_ADC_IC_1_MASK 0x100
|
||||
#define R13_WRITESPI_ADC_IC_1_SHIFT 8
|
||||
#define R13_MUTE_SERIALIN_IC_1_MASK 0x200
|
||||
#define R13_MUTE_SERIALIN_IC_1_SHIFT 9
|
||||
#define R13_GPIO_DEBOUNCE_IC_1_MASK 0xC00
|
||||
#define R13_GPIO_DEBOUNCE_IC_1_SHIFT 10
|
||||
#define R13_EXTMEM_SPEED_IC_1_MASK 0x3000
|
||||
#define R13_EXTMEM_SPEED_IC_1_SHIFT 12
|
||||
|
||||
/* RAMRegister (IC 1) */
|
||||
#define R14_RAM_MODULO_IC_1 0x8 /* 1000b [3:0] */
|
||||
#define R14_RAM_MODULO_IC_1_MASK 0xF
|
||||
#define R14_RAM_MODULO_IC_1_SHIFT 0
|
||||
|
||||
/* SerialOutRegister1 (IC 1) */
|
||||
#define R15_WORDLENGTH_IC_1 0x0 /* 00b [1:0] */
|
||||
#define R15_MSB_POS_IC_1 0x0 /* 000b [4:2] */
|
||||
#define R15_TDM_IC_1 0x0 /* 0b [5] */
|
||||
#define R15_FRAMESYNC_TYPE_IC_1 0x0 /* 0b [6] */
|
||||
#define R15_LRCLK_FREQ_IC_1 0x0 /* 00b [8:7] */
|
||||
#define R15_BCLK_FREQ_IC_1 0x0 /* 00b [10:9] */
|
||||
#define R15_MASTER_SLAVE_IC_1 0x1 /* 1b [11] */
|
||||
#define R15_BCLK_POLARITY_IC_1 0x0 /* 0b [12] */
|
||||
#define R15_LRCLK_POLARITY_IC_1 0x0 /* 0b [13] */
|
||||
#define R15_WORDLENGTH_IC_1_MASK 0x3
|
||||
#define R15_WORDLENGTH_IC_1_SHIFT 0
|
||||
#define R15_MSB_POS_IC_1_MASK 0x1C
|
||||
#define R15_MSB_POS_IC_1_SHIFT 2
|
||||
#define R15_TDM_IC_1_MASK 0x20
|
||||
#define R15_TDM_IC_1_SHIFT 5
|
||||
#define R15_FRAMESYNC_TYPE_IC_1_MASK 0x40
|
||||
#define R15_FRAMESYNC_TYPE_IC_1_SHIFT 6
|
||||
#define R15_LRCLK_FREQ_IC_1_MASK 0x180
|
||||
#define R15_LRCLK_FREQ_IC_1_SHIFT 7
|
||||
#define R15_BCLK_FREQ_IC_1_MASK 0x600
|
||||
#define R15_BCLK_FREQ_IC_1_SHIFT 9
|
||||
#define R15_MASTER_SLAVE_IC_1_MASK 0x800
|
||||
#define R15_MASTER_SLAVE_IC_1_SHIFT 11
|
||||
#define R15_BCLK_POLARITY_IC_1_MASK 0x1000
|
||||
#define R15_BCLK_POLARITY_IC_1_SHIFT 12
|
||||
#define R15_LRCLK_POLARITY_IC_1_MASK 0x2000
|
||||
#define R15_LRCLK_POLARITY_IC_1_SHIFT 13
|
||||
|
||||
/* SerialInputRegister (IC 1) */
|
||||
#define R16_INPUT_MODE_IC_1 0x0 /* 000b [2:0] */
|
||||
#define R16_BCLK_POLARITY_IC_1 0x0 /* 0b [3] */
|
||||
#define R16_LRCLK_POLARITY_IC_1 0x0 /* 0b [4] */
|
||||
#define R16_INPUT_MODE_IC_1_MASK 0x7
|
||||
#define R16_INPUT_MODE_IC_1_SHIFT 0
|
||||
#define R16_BCLK_POLARITY_IC_1_MASK 0x8
|
||||
#define R16_BCLK_POLARITY_IC_1_SHIFT 3
|
||||
#define R16_LRCLK_POLARITY_IC_1_MASK 0x10
|
||||
#define R16_LRCLK_POLARITY_IC_1_SHIFT 4
|
||||
|
||||
/* MpCfg0 (IC 1) */
|
||||
#define R17_MFSELECT0_IC_1 0x4 /* 100b [2:0] */
|
||||
#define R17_MFINVERT0_IC_1 0x0 /* 0b [3] */
|
||||
#define R17_MFSELECT1_IC_1 0x4 /* 100b [6:4] */
|
||||
#define R17_MFINVERT1_IC_1 0x0 /* 0b [7] */
|
||||
#define R17_MFSELECT2_IC_1 0x0 /* 000b [10:8] */
|
||||
#define R17_MFINVERT2_IC_1 0x0 /* 0b [11] */
|
||||
#define R17_MFSELECT3_IC_1 0x0 /* 000b [14:12] */
|
||||
#define R17_MFINVERT3_IC_1 0x0 /* 0b [15] */
|
||||
#define R17_MFSELECT4_IC_1 0x4 /* 100b [18:16] */
|
||||
#define R17_MFINVERT4_IC_1 0x0 /* 0b [19] */
|
||||
#define R17_MFSELECT5_IC_1 0x4 /* 100b [22:20] */
|
||||
#define R17_MFINVERT5_IC_1 0x0 /* 0b [23] */
|
||||
#define R17_MFSELECT0_IC_1_MASK 0x7
|
||||
#define R17_MFSELECT0_IC_1_SHIFT 0
|
||||
#define R17_MFINVERT0_IC_1_MASK 0x8
|
||||
#define R17_MFINVERT0_IC_1_SHIFT 3
|
||||
#define R17_MFSELECT1_IC_1_MASK 0x70
|
||||
#define R17_MFSELECT1_IC_1_SHIFT 4
|
||||
#define R17_MFINVERT1_IC_1_MASK 0x80
|
||||
#define R17_MFINVERT1_IC_1_SHIFT 7
|
||||
#define R17_MFSELECT2_IC_1_MASK 0x700
|
||||
#define R17_MFSELECT2_IC_1_SHIFT 8
|
||||
#define R17_MFINVERT2_IC_1_MASK 0x800
|
||||
#define R17_MFINVERT2_IC_1_SHIFT 11
|
||||
#define R17_MFSELECT3_IC_1_MASK 0x7000
|
||||
#define R17_MFSELECT3_IC_1_SHIFT 12
|
||||
#define R17_MFINVERT3_IC_1_MASK 0x8000
|
||||
#define R17_MFINVERT3_IC_1_SHIFT 15
|
||||
#define R17_MFSELECT4_IC_1_MASK 0x70000
|
||||
#define R17_MFSELECT4_IC_1_SHIFT 16
|
||||
#define R17_MFINVERT4_IC_1_MASK 0x80000
|
||||
#define R17_MFINVERT4_IC_1_SHIFT 19
|
||||
#define R17_MFSELECT5_IC_1_MASK 0x700000
|
||||
#define R17_MFSELECT5_IC_1_SHIFT 20
|
||||
#define R17_MFINVERT5_IC_1_MASK 0x800000
|
||||
#define R17_MFINVERT5_IC_1_SHIFT 23
|
||||
|
||||
/* MpCfg1 (IC 1) */
|
||||
#define R18_MFSELECT6_IC_1 0x4 /* 100b [2:0] */
|
||||
#define R18_MFINVERT6_IC_1 0x0 /* 0b [3] */
|
||||
#define R18_MFSELECT7_IC_1 0x0 /* 000b [6:4] */
|
||||
#define R18_MFINVERT7_IC_1 0x0 /* 0b [7] */
|
||||
#define R18_MFSELECT8_IC_1 0x0 /* 000b [10:8] */
|
||||
#define R18_MFINVERT8_IC_1 0x0 /* 0b [11] */
|
||||
#define R18_MFSELECT9_IC_1 0x0 /* 000b [14:12] */
|
||||
#define R18_MFINVERT9_IC_1 0x0 /* 0b [15] */
|
||||
#define R18_MFSELECT10_IC_1 0x4 /* 100b [18:16] */
|
||||
#define R18_MFINVERT10_IC_1 0x0 /* 0b [19] */
|
||||
#define R18_MFSELECT11_IC_1 0x4 /* 100b [22:20] */
|
||||
#define R18_MFINVERT11_IC_1 0x0 /* 0b [23] */
|
||||
#define R18_MFSELECT6_IC_1_MASK 0x7
|
||||
#define R18_MFSELECT6_IC_1_SHIFT 0
|
||||
#define R18_MFINVERT6_IC_1_MASK 0x8
|
||||
#define R18_MFINVERT6_IC_1_SHIFT 3
|
||||
#define R18_MFSELECT7_IC_1_MASK 0x70
|
||||
#define R18_MFSELECT7_IC_1_SHIFT 4
|
||||
#define R18_MFINVERT7_IC_1_MASK 0x80
|
||||
#define R18_MFINVERT7_IC_1_SHIFT 7
|
||||
#define R18_MFSELECT8_IC_1_MASK 0x700
|
||||
#define R18_MFSELECT8_IC_1_SHIFT 8
|
||||
#define R18_MFINVERT8_IC_1_MASK 0x800
|
||||
#define R18_MFINVERT8_IC_1_SHIFT 11
|
||||
#define R18_MFSELECT9_IC_1_MASK 0x7000
|
||||
#define R18_MFSELECT9_IC_1_SHIFT 12
|
||||
#define R18_MFINVERT9_IC_1_MASK 0x8000
|
||||
#define R18_MFINVERT9_IC_1_SHIFT 15
|
||||
#define R18_MFSELECT10_IC_1_MASK 0x70000
|
||||
#define R18_MFSELECT10_IC_1_SHIFT 16
|
||||
#define R18_MFINVERT10_IC_1_MASK 0x80000
|
||||
#define R18_MFINVERT10_IC_1_SHIFT 19
|
||||
#define R18_MFSELECT11_IC_1_MASK 0x700000
|
||||
#define R18_MFSELECT11_IC_1_SHIFT 20
|
||||
#define R18_MFINVERT11_IC_1_MASK 0x800000
|
||||
#define R18_MFINVERT11_IC_1_SHIFT 23
|
||||
|
||||
/* AnalogPowerDownRegister (IC 1) */
|
||||
#define R19_DAC3_POWERDOWN_IC_1 0x0 /* 0b [0] */
|
||||
#define R19_DAC2_POWERDOWN_IC_1 0x0 /* 0b [1] */
|
||||
#define R19_DAC1_POWERDOWN_IC_1 0x0 /* 0b [2] */
|
||||
#define R19_DAC0_POWERDOWN_IC_1 0x0 /* 0b [3] */
|
||||
#define R19_DACS_RESET_IC_1 0x0 /* 0b [4] */
|
||||
#define R19_REF_CORE_POWERDOWN_IC_1 0x0 /* 0b [5] */
|
||||
#define R19_REF_BUF_POWERDOWN_IC_1 0x0 /* 0b [6] */
|
||||
#define R19_ADCS_POWERDOWN_IC_1 0x0 /* 0b [7] */
|
||||
#define R19_AUX_ADC_FILTER_IC_1 0x0 /* 000b [10:8] */
|
||||
#define R19_DAC3_POWERDOWN_IC_1_MASK 0x1
|
||||
#define R19_DAC3_POWERDOWN_IC_1_SHIFT 0
|
||||
#define R19_DAC2_POWERDOWN_IC_1_MASK 0x2
|
||||
#define R19_DAC2_POWERDOWN_IC_1_SHIFT 1
|
||||
#define R19_DAC1_POWERDOWN_IC_1_MASK 0x4
|
||||
#define R19_DAC1_POWERDOWN_IC_1_SHIFT 2
|
||||
#define R19_DAC0_POWERDOWN_IC_1_MASK 0x8
|
||||
#define R19_DAC0_POWERDOWN_IC_1_SHIFT 3
|
||||
#define R19_DACS_RESET_IC_1_MASK 0x10
|
||||
#define R19_DACS_RESET_IC_1_SHIFT 4
|
||||
#define R19_REF_CORE_POWERDOWN_IC_1_MASK 0x20
|
||||
#define R19_REF_CORE_POWERDOWN_IC_1_SHIFT 5
|
||||
#define R19_REF_BUF_POWERDOWN_IC_1_MASK 0x40
|
||||
#define R19_REF_BUF_POWERDOWN_IC_1_SHIFT 6
|
||||
#define R19_ADCS_POWERDOWN_IC_1_MASK 0x80
|
||||
#define R19_ADCS_POWERDOWN_IC_1_SHIFT 7
|
||||
#define R19_AUX_ADC_FILTER_IC_1_MASK 0x700
|
||||
#define R19_AUX_ADC_FILTER_IC_1_SHIFT 8
|
||||
|
||||
/* TestRegister (IC 1) */
|
||||
#define R20_ADCCLOCKDELAY_IC_1 0x0 /* 000b [2:0] */
|
||||
#define R20_ADCSYNCFILTL_SDATAA_D_IC_1 0x0 /* 0b [3] */
|
||||
#define R20_ADCSYNCFILTR_SDATAA_D_IC_1 0x0 /* 0b [4] */
|
||||
#define R20_SPIKEFILT_SEROUT0_1_IC_1 0x0 /* 0b [5] */
|
||||
#define R20_UNUSED_IC_1 0x00 /* 0000000000b [15:6] */
|
||||
#define R20_ADCCLOCKDELAY_IC_1_MASK 0x7
|
||||
#define R20_ADCCLOCKDELAY_IC_1_SHIFT 0
|
||||
#define R20_ADCSYNCFILTL_SDATAA_D_IC_1_MASK 0x8
|
||||
#define R20_ADCSYNCFILTL_SDATAA_D_IC_1_SHIFT 3
|
||||
#define R20_ADCSYNCFILTR_SDATAA_D_IC_1_MASK 0x10
|
||||
#define R20_ADCSYNCFILTR_SDATAA_D_IC_1_SHIFT 4
|
||||
#define R20_SPIKEFILT_SEROUT0_1_IC_1_MASK 0x20
|
||||
#define R20_SPIKEFILT_SEROUT0_1_IC_1_SHIFT 5
|
||||
#define R20_UNUSED_IC_1_MASK 0xFFC0
|
||||
#define R20_UNUSED_IC_1_SHIFT 6
|
||||
|
||||
/* AnalogInterfaceRegister0 (IC 1) */
|
||||
#define R21_CHOP_ENB_INT_AMP_IC_1 0x0 /* 0b [0] */
|
||||
#define R21_PD_INT_AMP_IC_1 0x0 /* 0b [1] */
|
||||
#define R21_ADC_NON_OVERLAP_ADJ_IC_1 0x0 /* 0b [2] */
|
||||
#define R21_ADC_I_SEL_IC_1 0x0 /* 00000b [7:3] */
|
||||
#define R21_ADC_CLK_ADJ_IC_1 0x0 /* 000b [10:8] */
|
||||
#define R21_LCHOP_PMOS_CTRL_IC_1 0x0 /* 00b [12:11] */
|
||||
#define R21_LCHOP_AMP_ENB_IC_1 0x0 /* 0b [13] */
|
||||
#define R21_LSCRAM_ENB_IC_1 0x0 /* 0b [14] */
|
||||
#define R21_AUX_ADC_EN_IC_1 0x1 /* 1b [15] */
|
||||
#define R21_CHOP_ENB_INT_AMP_IC_1_MASK 0x1
|
||||
#define R21_CHOP_ENB_INT_AMP_IC_1_SHIFT 0
|
||||
#define R21_PD_INT_AMP_IC_1_MASK 0x2
|
||||
#define R21_PD_INT_AMP_IC_1_SHIFT 1
|
||||
#define R21_ADC_NON_OVERLAP_ADJ_IC_1_MASK 0x4
|
||||
#define R21_ADC_NON_OVERLAP_ADJ_IC_1_SHIFT 2
|
||||
#define R21_ADC_I_SEL_IC_1_MASK 0xF8
|
||||
#define R21_ADC_I_SEL_IC_1_SHIFT 3
|
||||
#define R21_ADC_CLK_ADJ_IC_1_MASK 0x700
|
||||
#define R21_ADC_CLK_ADJ_IC_1_SHIFT 8
|
||||
#define R21_LCHOP_PMOS_CTRL_IC_1_MASK 0x1800
|
||||
#define R21_LCHOP_PMOS_CTRL_IC_1_SHIFT 11
|
||||
#define R21_LCHOP_AMP_ENB_IC_1_MASK 0x2000
|
||||
#define R21_LCHOP_AMP_ENB_IC_1_SHIFT 13
|
||||
#define R21_LSCRAM_ENB_IC_1_MASK 0x4000
|
||||
#define R21_LSCRAM_ENB_IC_1_SHIFT 14
|
||||
#define R21_AUX_ADC_EN_IC_1_MASK 0x8000
|
||||
#define R21_AUX_ADC_EN_IC_1_SHIFT 15
|
||||
|
||||
/* AnalogInterfaceRegister1 (IC 1) */
|
||||
#define R22_RSWC_DAC_CTRL_IC_1 0x0 /* 00b [1:0] */
|
||||
#define R22_RCLK_SEL_PMOS_IC_1 0x0 /* 00b [3:2] */
|
||||
#define R22_RCLK_SEL_AMP_IC_1 0x0 /* 00b [5:4] */
|
||||
#define R22_RCHOP_PMOS_CTRL_IC_1 0x0 /* 00b [7:6] */
|
||||
#define R22_LCLK_SEL_PMOS_IC_1 0x0 /* 00b [9:8] */
|
||||
#define R22_LSWC_DAC_CTRL_IC_1 0x0 /* 00b [11:10] */
|
||||
#define R22_CLK_SEL_INT_AMP_IC_1 0x0 /* 00b [13:12] */
|
||||
#define R22_RSWC_DAC_CTRL_IC_1_MASK 0x3
|
||||
#define R22_RSWC_DAC_CTRL_IC_1_SHIFT 0
|
||||
#define R22_RCLK_SEL_PMOS_IC_1_MASK 0xC
|
||||
#define R22_RCLK_SEL_PMOS_IC_1_SHIFT 2
|
||||
#define R22_RCLK_SEL_AMP_IC_1_MASK 0x30
|
||||
#define R22_RCLK_SEL_AMP_IC_1_SHIFT 4
|
||||
#define R22_RCHOP_PMOS_CTRL_IC_1_MASK 0xC0
|
||||
#define R22_RCHOP_PMOS_CTRL_IC_1_SHIFT 6
|
||||
#define R22_LCLK_SEL_PMOS_IC_1_MASK 0x300
|
||||
#define R22_LCLK_SEL_PMOS_IC_1_SHIFT 8
|
||||
#define R22_LSWC_DAC_CTRL_IC_1_MASK 0xC00
|
||||
#define R22_LSWC_DAC_CTRL_IC_1_SHIFT 10
|
||||
#define R22_CLK_SEL_INT_AMP_IC_1_MASK 0x3000
|
||||
#define R22_CLK_SEL_INT_AMP_IC_1_SHIFT 12
|
||||
|
||||
/* AnalogInterfaceRegister2 (IC 1) */
|
||||
#define R23_UNUSED_IC_1 0x0 /* 0b [0] */
|
||||
#define R23_ADC_DITHER_EN_IC_1 0x0 /* 0b [1] */
|
||||
#define R23_XTAL_ENB_IC_1 0x0 /* 0b [2] */
|
||||
#define R23_PLL_PD_IC_1 0x0 /* 0b [3] */
|
||||
#define R23_IBIAS_TO_PIN_IC_1 0x0 /* 0b [4] */
|
||||
#define R23_IBIAS_ADJ_IC_1 0x0 /* 0000b [8:5] */
|
||||
#define R23_VREF_TRIM_IC_1 0x0 /* 0000b [12:9] */
|
||||
#define R23_REF_I_SEL_IC_1 0x0 /* 0b [13] */
|
||||
#define R23_RSCRAM_ENB_IC_1 0x0 /* 0b [14] */
|
||||
#define R23_LCHOP_AMP_ENB_IC_1 0x0 /* 0b [15] */
|
||||
#define R23_UNUSED_IC_1_MASK 0x1
|
||||
#define R23_UNUSED_IC_1_SHIFT 0
|
||||
#define R23_ADC_DITHER_EN_IC_1_MASK 0x2
|
||||
#define R23_ADC_DITHER_EN_IC_1_SHIFT 1
|
||||
#define R23_XTAL_ENB_IC_1_MASK 0x4
|
||||
#define R23_XTAL_ENB_IC_1_SHIFT 2
|
||||
#define R23_PLL_PD_IC_1_MASK 0x8
|
||||
#define R23_PLL_PD_IC_1_SHIFT 3
|
||||
#define R23_IBIAS_TO_PIN_IC_1_MASK 0x10
|
||||
#define R23_IBIAS_TO_PIN_IC_1_SHIFT 4
|
||||
#define R23_IBIAS_ADJ_IC_1_MASK 0x1E0
|
||||
#define R23_IBIAS_ADJ_IC_1_SHIFT 5
|
||||
#define R23_VREF_TRIM_IC_1_MASK 0x1E00
|
||||
#define R23_VREF_TRIM_IC_1_SHIFT 9
|
||||
#define R23_REF_I_SEL_IC_1_MASK 0x2000
|
||||
#define R23_REF_I_SEL_IC_1_SHIFT 13
|
||||
#define R23_RSCRAM_ENB_IC_1_MASK 0x4000
|
||||
#define R23_RSCRAM_ENB_IC_1_SHIFT 14
|
||||
#define R23_LCHOP_AMP_ENB_IC_1_MASK 0x8000
|
||||
#define R23_LCHOP_AMP_ENB_IC_1_SHIFT 15
|
||||
|
||||
/* AnalogInterfaceRegister3 (IC 1) */
|
||||
#define R24_DAC_OFFSET_IC_1 0x1 /* 01b [1:0] */
|
||||
#define R24_DAC_DITHER_ENABLE_IC_1 0x0 /* 0b [2] */
|
||||
#define R24_PCTRL_IC_1 0x0 /* 00b [4:3] */
|
||||
#define R24_DAC_PCLK_SEL_IC_1 0x0 /* 00b [6:5] */
|
||||
#define R24_DAC_I_SEL_IC_1 0x0 /* 0000b [10:7] */
|
||||
#define R24_DAC_CLK_SEL_IC_1 0x0 /* 00b [12:11] */
|
||||
#define R24_DAC_CHOP_ENB_IC_1 0x0 /* 0b [13] */
|
||||
#define R24_DAC_DRTZ_IC_1 0x0 /* 00b [15:14] */
|
||||
#define R24_DAC_OFFSET_IC_1_MASK 0x3
|
||||
#define R24_DAC_OFFSET_IC_1_SHIFT 0
|
||||
#define R24_DAC_DITHER_ENABLE_IC_1_MASK 0x4
|
||||
#define R24_DAC_DITHER_ENABLE_IC_1_SHIFT 2
|
||||
#define R24_PCTRL_IC_1_MASK 0x18
|
||||
#define R24_PCTRL_IC_1_SHIFT 3
|
||||
#define R24_DAC_PCLK_SEL_IC_1_MASK 0x60
|
||||
#define R24_DAC_PCLK_SEL_IC_1_SHIFT 5
|
||||
#define R24_DAC_I_SEL_IC_1_MASK 0x780
|
||||
#define R24_DAC_I_SEL_IC_1_SHIFT 7
|
||||
#define R24_DAC_CLK_SEL_IC_1_MASK 0x1800
|
||||
#define R24_DAC_CLK_SEL_IC_1_SHIFT 11
|
||||
#define R24_DAC_CHOP_ENB_IC_1_MASK 0x2000
|
||||
#define R24_DAC_CHOP_ENB_IC_1_SHIFT 13
|
||||
#define R24_DAC_DRTZ_IC_1_MASK 0xC000
|
||||
#define R24_DAC_DRTZ_IC_1_SHIFT 14
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,82 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!-- *
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright © 2026 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
-->
|
||||
<!--NetList XML file-->
|
||||
<NetList>
|
||||
<IC name=" IC 1 " type="DSPSigma100">
|
||||
<Schematic>
|
||||
<Algorithm name="ICSigma100In1" friendlyname="170x\140x input " cell="Input1 " location="{X=-15, Y=104} " Growth="10 " GrowthB="0 " FS="48000">
|
||||
<Link pin="O_C33_A0_P3_out" dir="out" link="Link0" />
|
||||
<Link pin="O_C33_A0_P4_out" dir="out" link="Link1" />
|
||||
<Link pin="O_C33_A0_P5_out" dir="out" link="Link2" />
|
||||
<Link pin="O_C33_A0_P6_out" dir="out" link="Link3" />
|
||||
</Algorithm>
|
||||
<Algorithm name="BeepAlg1" friendlyname="Beep - variable gain " cell="Beep1 " location="{X=933, Y=138} " Growth="0 " GrowthB="0 " FS="48000">
|
||||
<Link pin="O_C0_A0_P1_out" dir="out" link="Link15" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS1" friendlyname="Gain (no slew) " cell="Si4674 " location="{X=168, Y=5} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C63_A0_P1_in" dir="in" link="Link0" />
|
||||
<Link pin="O_C63_A0_P2_out" dir="out" link="Link4" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS2" friendlyname="Gain (no slew) " cell="Si4674 " location="{X=168, Y=5} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C63_A1_P1_in" dir="in" link="Link1" />
|
||||
<Link pin="O_C63_A1_P2_out" dir="out" link="Link5" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS3" friendlyname="Gain (no slew) " cell="ESP32 " location="{X=166, Y=196} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C75_A0_P1_in" dir="in" link="Link2" />
|
||||
<Link pin="O_C75_A0_P2_out" dir="out" link="Link6" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS4" friendlyname="Gain (no slew) " cell="ESP32 " location="{X=166, Y=196} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C75_A1_P1_in" dir="in" link="Link3" />
|
||||
<Link pin="O_C75_A1_P2_out" dir="out" link="Link7" />
|
||||
</Algorithm>
|
||||
<Algorithm name="ICSigma100Out1" friendlyname="170x\140x output " cell="Output1 " location="{X=1127, Y=55} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C183_A0_P1_in" dir="in" link="Link15" />
|
||||
</Algorithm>
|
||||
<Algorithm name="StereoMixerAlg1" friendlyname="Stereo Mixer " cell="St Mixer1 " location="{X=381, Y=115} " Growth="2 " GrowthB="0">
|
||||
<Link pin="I_C84_A0_P3_in" dir="in" link="Link4" />
|
||||
<Link pin="I_C84_A0_P4_in" dir="in" link="Link5" />
|
||||
<Link pin="I_C84_A0_P5_in" dir="in" link="Link6" />
|
||||
<Link pin="I_C84_A0_P6_in" dir="in" link="Link7" />
|
||||
<Link pin="O_C84_A0_P1_out" dir="out" link="Link8" />
|
||||
<Link pin="O_C84_A0_P2_out" dir="out" link="Link9" />
|
||||
</Algorithm>
|
||||
<Algorithm name="PEQ1Chan1" friendlyname="PEQ1Chan - Double Precision " cell="Param EQ1 " location="{X=502, Y=156} " Growth="2 " GrowthB="0">
|
||||
<Link pin="I_C125_A0_P1_in" dir="in" link="Link8" />
|
||||
<Link pin="I_C125_A0_P3_in" dir="in" link="Link9" />
|
||||
<Link pin="O_C125_A0_P2_out" dir="out" link="Link10" />
|
||||
<Link pin="O_C125_A0_P4_out" dir="out" link="Link11" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS5" friendlyname="Gain (no slew) " cell="Multiple 1 " location="{X=628, Y=88} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C138_A0_P1_in" dir="in" link="Link10" />
|
||||
<Link pin="O_C138_A0_P2_out" dir="out" link="Link12" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS6" friendlyname="Gain (no slew) " cell="Multiple 1 " location="{X=628, Y=88} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C138_A1_P1_in" dir="in" link="Link11" />
|
||||
<Link pin="O_C138_A1_P2_out" dir="out" link="Link13" />
|
||||
</Algorithm>
|
||||
<Algorithm name="limiterAlg1" friendlyname="Limiter with Indicator " cell="Limiter 1 " location="{X=761, Y=40} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C169_A0_P1_in" dir="in" link="Link12" />
|
||||
</Algorithm>
|
||||
<Algorithm name="limiterAlg2" friendlyname="Limiter with Indicator " cell="Limiter 2 " location="{X=765, Y=189} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C174_A0_P1_in" dir="in" link="Link13" />
|
||||
<Link pin="O_C174_A0_P2_out" dir="out" link="Link14" />
|
||||
</Algorithm>
|
||||
<Algorithm name="ICSigma100Out2" friendlyname="170x\140x output " cell="Output2 " location="{X=890, Y=227} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C185_A0_P1_in" dir="in" link="Link14" />
|
||||
</Algorithm>
|
||||
</Schematic>
|
||||
</IC>
|
||||
</NetList>
|
||||
@@ -0,0 +1,5 @@
|
||||
4,
|
||||
5122,
|
||||
4098,
|
||||
26,
|
||||
4,
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* File: defines.h
|
||||
*
|
||||
* Created: Thursday, August 6, 2026 1:57:25 PM
|
||||
* Description: DigiRadio IC default download data definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2026 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __DEFINES_H__
|
||||
#define __DEFINES_H__
|
||||
|
||||
#define BufferSize_IC_1 9254
|
||||
#define NumTransactions_IC_1 5
|
||||
|
||||
|
||||
#endif
|
||||
Binary file not shown.
Binary file not shown.
Reference in New Issue
Block a user