Harden Si4684 RSTB config and document power sequencing.
Enable GPIO_PULLDOWN_ENABLE during gpio_config so RSTB cannot glitch high before gpio_set_level(0), and add manual validation notes explaining why the internal pull-down complements the external one. Co-authored-by: Cursor <cursoragent@cursor.com>
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Cursor
@@ -327,3 +327,162 @@ The GPIO and I\textsuperscript{2}C maps are complete and match
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This section is the authoritative wiring reference for firmware bring-up:
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the pin definitions in the source code must match it exactly.
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\section{Design validation and critical checks}
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\label{sec:hw-validation}
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This section records the design-review checks performed against the
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component datasheets before fabrication, chip by chip. Items marked
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\emph{critical} can cause permanent damage or a non-functional board if
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violated, and were verified explicitly.
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\subsection{Si4684 tuner}
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\label{sec:hw-val-si4684}
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\begin{drcaution}[Critical --- RSTB and power sequencing]
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The Si4684 datasheet requires that RSTB be held low during any power-supply
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transition and remain asserted for 10\,\textmu s after all supplies are
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stable; failing to do so \emph{may permanently damage the device}. On
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DigiRadio, RSTB (GPIO38) has an external pull-down, so the chip powers up
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held in reset until the ESP32 releases it. \textbf{Verified.} The firmware
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must not drive RSTB high before the Si4684 supplies are stable.
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\end{drcaution}
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\begin{drnote}[Firmware bring-up]
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RSTB is driven only in \texttt{Si4684Driver::boot()}
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(Chapter~\ref{ch:si4684}): GPIO38 is configured as output with
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\texttt{GPIO\_PULLDOWN\_ENABLE} so the net cannot glitch high while the pin
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mode changes, then held low for 5\,ms and released. The internal pull-down
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is \emph{not} redundant with the external resistor: the external pull-down
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holds RSTB during board power-on before \texttt{app\_main}; the internal one
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closes the brief window between \texttt{gpio\_config} and
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\texttt{gpio\_set\_level(0)} where an output register default could otherwise
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violate the datasheet sequencing rule. No other code touches GPIO38. Release
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occurs only after all Si4684 supplies (VA, VIO, VCORE, VMEM) are stable,
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satisfying the +10\,\textmu s requirement in practice.
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\end{drnote}
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\begin{table}[htbp]
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\centering
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\small
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\begin{tabular}{@{}lll@{}}
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\drhead Check & Requirement (datasheet) & Status \\
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\midrule
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RSTB low at power-up & held low until supplies stable +10\,\textmu s & verified (pull-down) \\
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RSTB release (firmware) & not before supplies stable; boot pulse only & verified (driver) \\
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RSTB glitch guard (firmware) & \texttt{GPIO\_PULLDOWN\_ENABLE} in \texttt{gpio\_config} & verified (driver) \\
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Core supplies at 1.8\,V & VA = VCORE = VMEM = 1.8\,V & verified \\
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VIO level & 1.62--3.6\,V (3.3\,V to talk to ESP32) & verified \\
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Bypass caps & 2.2\,nF + 1\,\textmu F per VIO/VMEM/VCORE rail & verified \\
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SPI mode & Mode 0 or 3, up to 10\,MHz, SMODE = GND & verified \\
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SSB framing (firmware) & SSB held low for the whole transaction & driver rule \\
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INTB & interrupt line, external pull-up (GPIO39) & verified \\
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\bottomrule
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\end{tabular}
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\caption{Si4684 design checks. References: Si4684-A10 datasheet
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(power sequencing, SPI, supply levels) and AN851 (bypass and layout).}
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\label{tab:hw-val-si4684}
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\end{table}
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\begin{drref}[Datasheet]
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Power sequencing and SPI framing: Si4684-A10 data sheet. The user must not
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pulse SSB high between bytes; SSB frames the whole command/reply.
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Bypass-capacitor values and placement: AN851, \emph{Si468x Schematic and
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Layout Guide}. Boot and command protocol: AN649.
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\end{drref}
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The core, memory, and analogue rails run at 1.8\,V; only VIO is at 3.3\,V
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to interface the ESP32. The 2.2\,nF and 1\,\textmu F bypass pairs are
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placed close to VIO (pin~34), VMEM (pin~35), and VCORE (pin~37) as AN851
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requires. The VHF antenna input follows the AN851 layout guidance (short,
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narrow microstrip; ground-fill relief; ferrite beads near the connector).
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\subsection{ADAU1701 DSP}
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\label{sec:hw-val-adau}
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\begin{drkey}[Master-clock loopback is mandatory, not optional]
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For an ADAU1701 operating as I\textsuperscript{2}S master while receiving
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data on its serial inputs, the datasheet requires OUTPUT\_LRCLK (MP10) and
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OUTPUT\_BCLK (MP11) to be set to master mode and \emph{connected externally}
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to INPUT\_LRCLK (MP4) and INPUT\_BCLK (MP5). DigiRadio wires exactly this
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loopback (MP10$\rightarrow$MP4, MP11$\rightarrow$MP5). Without it the DSP
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locks up when input data arrives.
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\end{drkey}
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\begin{table}[htbp]
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\centering
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\small
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\begin{tabular}{@{}lll@{}}
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\drhead Check & Requirement (datasheet) & Status \\
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\midrule
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Clock loopback & MP10$\rightarrow$MP4, MP11$\rightarrow$MP5 wired & verified \\
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Output master & serial output port in Master Mode & verified \\
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MCLK ratio & exactly 256\,$\times$\,f\textsubscript{S} & verified \\
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MCLK value & 12.288\,MHz oscillator (256\,$\times$\,48\,kHz) & verified \\
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I\textsuperscript{2}C pull-ups & 2.2\,k\(\Omega\) on SDA and SCL & to verify \\
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I\textsuperscript{2}C address & 0x34 (ADDR0 = ADDR1 = GND) & verified \\
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Self-boot & disabled (host RAM load) & verified \\
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\bottomrule
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\end{tabular}
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\caption{ADAU1701 design checks. Reference: ADAU1701 data sheet (Rev.~C),
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serial-port master/slave section and I\textsuperscript{2}C port.}
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\label{tab:hw-val-adau}
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\end{table}
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\begin{drref}[Datasheet]
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Master-clock loopback and serial-port modes: ADAU1701 data sheet, Rev.~C,
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Table~63 and the serial-port section. The master clock must be exactly
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256\,$\times$\,f\textsubscript{S}. I\textsuperscript{2}C lines require
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2.2\,k\(\Omega\) pull-ups.
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\end{drref}
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\begin{drcaution}[Open item --- I\textsuperscript{2}C pull-ups]
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The ADAU1701 datasheet requires 2.2\,k\(\Omega\) pull-up resistors on SDA
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and SCL. Confirm these are present on the board (shared bus with the
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EEPROM); this is the one ADAU check still to close.
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\end{drcaution}
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\subsection{FSC-BT1035 (QCC3056)}
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\label{sec:hw-val-bt1035}
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\begin{table}[htbp]
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\centering
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\small
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\begin{tabular}{@{}lll@{}}
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\drhead Check & Requirement & Status \\
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\midrule
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UART with flow control & TX/RX + RTS/CTS wired & verified \\
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Line-In enable (firmware) & \texttt{AT+AUXCFG=1} in init & driver rule \\
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I\textsuperscript{2}S input & receives clocks from ADAU master (slave) & verified \\
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Reset line & RESET (GPIO17) driven by ESP32 & verified \\
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\bottomrule
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\end{tabular}
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\caption{FSC-BT1035 design checks. The module is an I\textsuperscript{2}S
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slave fed by the ADAU master; audio arrives on its I\textsuperscript{2}S
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input pins.}
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\label{tab:hw-val-bt1035}
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\end{table}
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\subsection{System-level summary}
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\label{sec:hw-val-summary}
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\begin{table}[htbp]
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\centering
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\begin{tabular}{@{}lll@{}}
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\drhead Area & Item & Status \\
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\midrule
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Si4684 & RSTB pull-down, 1.8\,V rails, bypass caps, SPI & verified \\
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Si4684 & RSTB release only in \texttt{Si4684Driver::boot()} & verified \\
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ADAU1701 & clock loopback, master mode, 256$\times$f\textsubscript{S} & verified \\
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ADAU1701 & I\textsuperscript{2}C 2.2\,k\(\Omega\) pull-ups & to verify \\
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FSC-BT1035 & UART + flow control, I\textsuperscript{2}S slave & verified \\
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Clocking & single 48\,kHz domain, ADAU master & verified \\
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\bottomrule
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\end{tabular}
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\caption{Consolidated pre-fabrication validation status.}
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\label{tab:hw-val-summary}
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\end{table}
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The only open hardware check is the presence of the 2.2\,k\(\Omega\)
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I\textsuperscript{2}C pull-ups on the ADAU/EEPROM bus. All damage-class
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items (Si4684 power sequencing and supply levels) are verified.
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