Release fw 0.8.5: BT1035 I2S boot init and hardware doc alignment.
Switch BT1035 bring-up from Line-In to I2S slave (AT+AUXCFG=3, AT+I2SCFG=67) to match the ADAU1701 PCM routing, confirm 2 kΩ I2C pull-ups on R1/R16, and sync firmware docs, AGENTS rules, and the DATASHEET bundle. Co-authored-by: Cursor <cursoragent@cursor.com>
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Cursor
@@ -128,11 +128,11 @@ control (RTS/CTS). The host sends commands and parses the module's
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responses explicitly, treating timeouts as errors. Some settings are held
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in the module's own non-volatile memory.
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\begin{drcaution}[Line-In mode]
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The initialisation sequence must enable Line-In mode (\texttt{AT+AUXCFG=1})
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so the module accepts the wired audio coming from the DSP. Omitting it
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silently breaks the audio path. Driver boot flow and AT subset are documented
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in Chapter~\ref{ch:bt1035}.
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\begin{drcaution}[I\textsuperscript{2}S slave mode]
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The PCB routes ADAU1701 \texttt{SDATA\_OUT0} to the module over
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I\textsuperscript{2}S (BCLK, LRCLK, PCM data). Firmware must initialise
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\texttt{AT+AUXCFG=3} and \texttt{AT+I2SCFG=67}, not Line-In
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(\texttt{AT+AUXCFG=1}). See Chapter~\ref{ch:bt1035}, Section~\ref{sec:bt1035-i2s}.
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\end{drcaution}
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\section{The host: ESP32-S3}
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@@ -379,16 +379,19 @@ satisfying the +10\,\textmu s requirement in practice.
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INTB & interrupt line, external pull-up (GPIO39) & verified \\
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\bottomrule
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\end{tabular}
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\caption{Si4684 design checks. References: Si4684-A10 datasheet
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(power sequencing, SPI, supply levels) and AN851 (bypass and layout).}
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\caption{Si4684 design checks. References:
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\texttt{Hardware/DATASHEET/SI4684-A10.pdf} (power sequencing, SPI,
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supply levels) and \texttt{Hardware/DATASHEET/AN851.pdf} (bypass and layout).}
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\label{tab:hw-val-si4684}
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\end{table}
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\begin{drref}[Datasheet]
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Power sequencing and SPI framing: Si4684-A10 data sheet. The user must not
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pulse SSB high between bytes; SSB frames the whole command/reply.
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Bypass-capacitor values and placement: AN851, \emph{Si468x Schematic and
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Layout Guide}. Boot and command protocol: AN649.
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Power sequencing and SPI framing:
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\texttt{Hardware/DATASHEET/SI4684-A10.pdf}. The user must not pulse SSB high
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between bytes; SSB frames the whole command/reply.
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Bypass-capacitor values and placement: \texttt{Hardware/DATASHEET/AN851.pdf},
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\emph{Si468x Schematic and Layout Guide}. Boot and command protocol: AN649.
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Local copies: \texttt{Hardware/DATASHEET/} (see \texttt{README.md}).
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\end{drref}
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The core, memory, and analogue rails run at 1.8\,V; only VIO is at 3.3\,V
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@@ -419,7 +422,7 @@ locks up when input data arrives.
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Output master & serial output port in Master Mode & verified \\
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MCLK ratio & exactly 256\,$\times$\,f\textsubscript{S} & verified \\
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MCLK value & 12.288\,MHz oscillator (256\,$\times$\,48\,kHz) & verified \\
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I\textsuperscript{2}C pull-ups & 2.2\,k\(\Omega\) on SDA and SCL & to verify \\
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I\textsuperscript{2}C pull-ups & 2\,k\(\Omega\) on SDA/SCL (R16/R1) & verified \\
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I\textsuperscript{2}C address & 0x34 (ADDR0 = ADDR1 = GND) & verified \\
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Self-boot & disabled (host RAM load) & verified \\
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\bottomrule
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@@ -430,17 +433,18 @@ locks up when input data arrives.
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\end{table}
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\begin{drref}[Datasheet]
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Master-clock loopback and serial-port modes: ADAU1701 data sheet, Rev.~C,
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Table~63 and the serial-port section. The master clock must be exactly
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256\,$\times$\,f\textsubscript{S}. I\textsuperscript{2}C lines require
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2.2\,k\(\Omega\) pull-ups.
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Master-clock loopback and serial-port modes:
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\texttt{Hardware/DATASHEET/adau1701.pdf}, Rev.~C, Table~63 and the serial-port
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section. The master clock must be exactly 256\,$\times$\,f\textsubscript{S}.
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I\textsuperscript{2}C lines require pull-up resistors on SDA and SCL.
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DigiRadio uses \textbf{2\,k\(\Omega\)} (schematic R1/R16; ADAU1701 datasheet
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recommends 2.2\,k\(\Omega\) --- acceptable at 3.3\,V).
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\end{drref}
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\begin{drcaution}[Open item --- I\textsuperscript{2}C pull-ups]
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The ADAU1701 datasheet requires 2.2\,k\(\Omega\) pull-up resistors on SDA
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and SCL. Confirm these are present on the board (shared bus with the
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EEPROM); this is the one ADAU check still to close.
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\end{drcaution}
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\begin{drnote}[I\textsuperscript{2}C pull-ups confirmed]
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Schematic \texttt{DigitalRadio.pdf} and BOM list R1 (SCL) and R16 (SDA) as
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2\,k\(\Omega\) to 3V3 on the shared ADAU1701/EEPROM bus.
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\end{drnote}
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\subsection{FSC-BT1035 (QCC3056)}
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\label{sec:hw-val-bt1035}
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@@ -452,17 +456,24 @@ EEPROM); this is the one ADAU check still to close.
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\drhead Check & Requirement & Status \\
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\midrule
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UART with flow control & TX/RX + RTS/CTS wired & verified \\
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Line-In enable (firmware) & \texttt{AT+AUXCFG=1} in init & driver rule \\
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I\textsuperscript{2}S init (firmware) & \texttt{AT+AUXCFG=3}, \texttt{AT+I2SCFG=67} & driver rule \\
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I\textsuperscript{2}S input & receives clocks from ADAU master (slave) & verified \\
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Reset line & RESET (GPIO17) driven by ESP32 & verified \\
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\bottomrule
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\end{tabular}
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\caption{FSC-BT1035 design checks. The module is an I\textsuperscript{2}S
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slave fed by the ADAU master; audio arrives on its I\textsuperscript{2}S
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input pins.}
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\caption{FSC-BT1035 design checks. Datasheet:
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\texttt{Hardware/DATASHEET/FSC-BT1035\_Datasheet\_EN.pdf}; AT commands:
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\texttt{FSC-BT1035\_programming\_user\_guide\_1.1.1.pdf} §5.}
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\label{tab:hw-val-bt1035}
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\end{table}
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\begin{drref}[Programming guide defaults]
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Module defaults (Feasycom release 1.1.1): BR/EDR name \texttt{FSC-BT1035},
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UART 115200/8/N/1, SSP on, auto-reconnect configurable via
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\texttt{AT+AUTOCONN=0..15}. DigiRadio overrides the name from EEPROM identity
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(\texttt{AT+NAME=<name>,0} disables the module MAC suffix).
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\end{drref}
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\subsection{System-level summary}
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\label{sec:hw-val-summary}
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@@ -474,7 +485,7 @@ EEPROM); this is the one ADAU check still to close.
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Si4684 & RSTB pull-down, 1.8\,V rails, bypass caps, SPI & verified \\
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Si4684 & RSTB release only in \texttt{Si4684Driver::boot()} & verified \\
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ADAU1701 & clock loopback, master mode, 256$\times$f\textsubscript{S} & verified \\
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ADAU1701 & I\textsuperscript{2}C 2.2\,k\(\Omega\) pull-ups & to verify \\
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ADAU1701 & I\textsuperscript{2}C 2\,k\(\Omega\) pull-ups (R1/R16) & verified \\
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FSC-BT1035 & UART + flow control, I\textsuperscript{2}S slave & verified \\
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Clocking & single 48\,kHz domain, ADAU master & verified \\
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\bottomrule
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@@ -483,6 +494,6 @@ EEPROM); this is the one ADAU check still to close.
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\label{tab:hw-val-summary}
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\end{table}
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The only open hardware check is the presence of the 2.2\,k\(\Omega\)
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I\textsuperscript{2}C pull-ups on the ADAU/EEPROM bus. All damage-class
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items (Si4684 power sequencing and supply levels) are verified.
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The consolidated pre-fabrication validation is complete for all
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damage-class items (Si4684 power sequencing and supply levels) and the
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shared I\textsuperscript{2}C bus.
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